mp8086.eda.rpt

来自「X8086的VHDL源码」· RPT 代码 · 共 58 行

EDA Netlist Writer report for MP8086
Tue Jan 09 23:45:12 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. EDA Netlist Writer Messages



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; Legal Notice ;
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Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Tue Jan 09 23:45:12 2007 ;
; Revision Name             ; MP8086                                ;
; Top-level Entity Name     ; MP8086                                ;
; Family                    ; Stratix                               ;
+---------------------------+---------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Jan 09 23:45:03 2007
Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off MP8086 -c MP8086 --gen_testbench
Info: Generated VHDL Test Bench File C:/work/MP8086/simulation/modelsim/MP8086.vht for simulation
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Jan 09 23:45:12 2007
    Info: Elapsed time: 00:00:28