mp8086.tan.rpt

X8086的VHDL源码

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP20K400EBC652-3   ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; I_CLK           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'I_CLK'                                                                                                                                                                                                                                                                                                                                                 ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                        ; To                                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 9.13 MHz ( period = 109.548 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[121]          ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.661 ns               ;
; N/A                                     ; 9.13 MHz ( period = 109.476 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[451]          ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.610 ns               ;
; N/A                                     ; 9.14 MHz ( period = 109.426 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[451]          ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[6]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.585 ns               ;
; N/A                                     ; 9.15 MHz ( period = 109.280 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[74]           ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.539 ns               ;
; N/A                                     ; 9.15 MHz ( period = 109.248 ns )                    ; BIU:T_BIU_MP8086|FETCH:T_FETCH_BIU|FIFO:FIFO_FETCH|rp_i[2]  ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.499 ns               ;
; N/A                                     ; 9.17 MHz ( period = 109.004 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[106]          ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.404 ns               ;
; N/A                                     ; 9.18 MHz ( period = 108.954 ns )                    ; CUEU:T_CUEU_MP8086|EUC:EUC_CUEU|current_state[106]          ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[6]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.379 ns               ;
; N/A                                     ; 9.19 MHz ( period = 108.800 ns )                    ; CUEU:T_CUEU_MP8086|EU:T_EU_CUEU|TRU:TRU_EU|O_REG2_0         ; LMEM:LMEM_MP8086|lpm_ram_dpZ0:lpm_ram_dp_component|lpm_ram_dp:U1|altdpram:sram|q[0]~reg_in ; I_CLK      ; I_CLK    ; None                        ; None                      ; 54.278 ns               ;