📄 mp8086.vht
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ***************************************************************************
-- This file contains a Vhdl test bench template that is freely editable to
-- suit user's needs .Comments are provided in each section to help the user
-- fill out necessary details.
-- ***************************************************************************
-- Generated on "01/09/2007 23:45:11"
-- Vhdl Test Bench template for design : MP8086
--
-- Simulation tool : ModelSim (VHDL)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY MP8086_vhd_tst IS
END MP8086_vhd_tst;
ARCHITECTURE MP8086_arch OF MP8086_vhd_tst IS
-- constants
-- signals
SIGNAL t_sig_I_CLK : STD_LOGIC;
SIGNAL t_sig_I_RST : STD_LOGIC;
SIGNAL t_sig_I_RDY : STD_LOGIC;
SIGNAL t_sig_I_S77 : STD_LOGIC;
SIGNAL t_sig_O_ALUDATA_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_AX_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_CX_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_BX_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_DX_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_SP_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_BP_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_SI_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_DI_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_EUCSTATE_V : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL t_sig_O_BCUSTATE_V : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL t_sig_O_EACUSTATE : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL t_sig_O_DIVSTATE : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL t_sig_O_DCSTATE_V : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL t_sig_O_FREG : STD_LOGIC_VECTOR(8 downto 0);
SIGNAL t_sig_O_DS_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_ES_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_SS_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_CS_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_MOD : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL t_sig_O_RM : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL t_sig_O_QUEFULL : STD_LOGIC;
SIGNAL t_sig_O_DEN_N : STD_LOGIC;
SIGNAL t_sig_O_DTR : STD_LOGIC;
SIGNAL t_sig_O_NOP_V : STD_LOGIC;
SIGNAL t_sig_O_IO : STD_LOGIC;
SIGNAL t_sig_O_TYPEZERO : STD_LOGIC;
SIGNAL t_sig_O_EARQ : STD_LOGIC;
SIGNAL t_sig_O_BDATA : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_ADR_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_BCUEXTBUS_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_MCUEXTBUS_V : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_DATAH_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_DATAL_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA1 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA2 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA3 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA4 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA5 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA6 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA7 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_7SEGDATA8 : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_WRH_V : STD_LOGIC;
SIGNAL t_sig_O_WRL_V : STD_LOGIC;
SIGNAL t_sig_O_OP_V : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL t_sig_O_REG1 : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL t_sig_O_REG2 : STD_LOGIC_VECTOR(15 downto 0);
COMPONENT MP8086
PORT (
I_CLK : in STD_LOGIC;
I_RST : in STD_LOGIC;
I_RDY : in STD_LOGIC;
I_S77 : in STD_LOGIC;
O_ALUDATA_V : out STD_LOGIC_VECTOR(15 downto 0);
O_AX_V : out STD_LOGIC_VECTOR(15 downto 0);
O_CX_V : out STD_LOGIC_VECTOR(15 downto 0);
O_BX_V : out STD_LOGIC_VECTOR(15 downto 0);
O_DX_V : out STD_LOGIC_VECTOR(15 downto 0);
O_SP_V : out STD_LOGIC_VECTOR(15 downto 0);
O_BP_V : out STD_LOGIC_VECTOR(15 downto 0);
O_SI_V : out STD_LOGIC_VECTOR(15 downto 0);
O_DI_V : out STD_LOGIC_VECTOR(15 downto 0);
O_EUCSTATE_V : out STD_LOGIC_VECTOR(8 downto 0);
O_BCUSTATE_V : out STD_LOGIC_VECTOR(2 downto 0);
O_EACUSTATE : out STD_LOGIC_VECTOR(2 downto 0);
O_DIVSTATE : out STD_LOGIC_VECTOR(3 downto 0);
O_DCSTATE_V : out STD_LOGIC_VECTOR(3 downto 0);
O_FREG : out STD_LOGIC_VECTOR(8 downto 0);
O_DS_V : out STD_LOGIC_VECTOR(15 downto 0);
O_ES_V : out STD_LOGIC_VECTOR(15 downto 0);
O_SS_V : out STD_LOGIC_VECTOR(15 downto 0);
O_CS_V : out STD_LOGIC_VECTOR(15 downto 0);
O_MOD : out STD_LOGIC_VECTOR(1 downto 0);
O_RM : out STD_LOGIC_VECTOR(2 downto 0);
O_QUEFULL : out STD_LOGIC;
O_DEN_N : out STD_LOGIC;
O_DTR : out STD_LOGIC;
O_NOP_V : out STD_LOGIC;
O_IO : out STD_LOGIC;
O_TYPEZERO : out STD_LOGIC;
O_EARQ : out STD_LOGIC;
O_BDATA : out STD_LOGIC_VECTOR(7 downto 0);
O_ADR_V : out STD_LOGIC_VECTOR(7 downto 0);
O_BCUEXTBUS_V : out STD_LOGIC_VECTOR(15 downto 0);
O_MCUEXTBUS_V : out STD_LOGIC_VECTOR(15 downto 0);
O_DATAH_V : out STD_LOGIC_VECTOR(7 downto 0);
O_DATAL_V : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA1 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA2 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA3 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA4 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA5 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA6 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA7 : out STD_LOGIC_VECTOR(7 downto 0);
O_7SEGDATA8 : out STD_LOGIC_VECTOR(7 downto 0);
O_WRH_V : out STD_LOGIC;
O_WRL_V : out STD_LOGIC;
O_OP_V : out STD_LOGIC_VECTOR(7 downto 0);
O_REG1 : out STD_LOGIC_VECTOR(15 downto 0);
O_REG2 : out STD_LOGIC_VECTOR(15 downto 0) );
END COMPONENT;
BEGIN
i1 : MP8086 PORT MAP (
-- list connections between master ports and signals
I_CLK => t_sig_I_CLK,
I_RST => t_sig_I_RST,
I_RDY => t_sig_I_RDY,
I_S77 => t_sig_I_S77,
O_ALUDATA_V => t_sig_O_ALUDATA_V,
O_AX_V => t_sig_O_AX_V,
O_CX_V => t_sig_O_CX_V,
O_BX_V => t_sig_O_BX_V,
O_DX_V => t_sig_O_DX_V,
O_SP_V => t_sig_O_SP_V,
O_BP_V => t_sig_O_BP_V,
O_SI_V => t_sig_O_SI_V,
O_DI_V => t_sig_O_DI_V,
O_EUCSTATE_V => t_sig_O_EUCSTATE_V,
O_BCUSTATE_V => t_sig_O_BCUSTATE_V,
O_EACUSTATE => t_sig_O_EACUSTATE,
O_DIVSTATE => t_sig_O_DIVSTATE,
O_DCSTATE_V => t_sig_O_DCSTATE_V,
O_FREG => t_sig_O_FREG,
O_DS_V => t_sig_O_DS_V,
O_ES_V => t_sig_O_ES_V,
O_SS_V => t_sig_O_SS_V,
O_CS_V => t_sig_O_CS_V,
O_MOD => t_sig_O_MOD,
O_RM => t_sig_O_RM,
O_QUEFULL => t_sig_O_QUEFULL,
O_DEN_N => t_sig_O_DEN_N,
O_DTR => t_sig_O_DTR,
O_NOP_V => t_sig_O_NOP_V,
O_IO => t_sig_O_IO,
O_TYPEZERO => t_sig_O_TYPEZERO,
O_EARQ => t_sig_O_EARQ,
O_BDATA => t_sig_O_BDATA,
O_ADR_V => t_sig_O_ADR_V,
O_BCUEXTBUS_V => t_sig_O_BCUEXTBUS_V,
O_MCUEXTBUS_V => t_sig_O_MCUEXTBUS_V,
O_DATAH_V => t_sig_O_DATAH_V,
O_DATAL_V => t_sig_O_DATAL_V,
O_7SEGDATA1 => t_sig_O_7SEGDATA1,
O_7SEGDATA2 => t_sig_O_7SEGDATA2,
O_7SEGDATA3 => t_sig_O_7SEGDATA3,
O_7SEGDATA4 => t_sig_O_7SEGDATA4,
O_7SEGDATA5 => t_sig_O_7SEGDATA5,
O_7SEGDATA6 => t_sig_O_7SEGDATA6,
O_7SEGDATA7 => t_sig_O_7SEGDATA7,
O_7SEGDATA8 => t_sig_O_7SEGDATA8,
O_WRH_V => t_sig_O_WRH_V,
O_WRL_V => t_sig_O_WRL_V,
O_OP_V => t_sig_O_OP_V,
O_REG1 => t_sig_O_REG1,
O_REG2 => t_sig_O_REG2
);
init : PROCESS
-- variable declarations
BEGIN
-- code that executes only once
WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END MP8086_arch;
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