dtmpx.vhd

X8086的VHDL源码

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--   FILE NAME : DT_MPX_BIU.vhd
--   FUNCTION  : select DATA (REGISTAR or MEMORY)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 9/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DTMPX is
    port( I_EUDATA   :  in std_logic_vector(15 downto 0 ); --DATA from EA
	      I_WRIP     :  in std_logic; --write signal to IP
		  I_WRIR     :  in std_logic; --write signal to IR
		  I_WRSR     :  in std_logic; --write signal to Segment REGISTAR
		  I_EARQ     :  in std_logic; --EA out => '1'
		  I_EUCDATA  :  in std_logic_vector(15 downto 0 ); --EUC DATA
		  I_2BIU     :  in std_logic; --EUC DATA to BIU signal
		  I_2SR      :  in std_logic; --EUC DATA(address) to Segment Registar
          O_DATA2SR  : out std_logic_vector(15 downto 0 ); --OUTPUT DATA to REGISTAR
          O_DATA2MEM : out std_logic_vector(15 downto 0 ) --OUTPUT DATA to MEMORY
		  );
end DTMPX;

architecture RTL of DTMPX is

begin
	process(I_EUDATA,I_WRIP,I_WRSR,I_WRIR,I_EARQ,I_2BIU,I_EUCDATA,I_2SR)
	begin
		if ((I_WRIP = '1' or I_WRIR = '1') or (I_WRSR = '1' or I_EARQ='1'))then --when write to registar 
			O_DATA2MEM <= I_EUDATA;
			if (I_2SR = '1')then
				O_DATA2SR <= I_EUCDATA;
			else
				O_DATA2SR <= I_EUDATA;
			end if;
		else
			O_DATA2SR <= I_EUDATA;
			if (I_2BIU='1')then --EUC DATA to BIU 
				O_DATA2MEM <= I_EUCDATA;
			else
				O_DATA2MEM <= I_EUDATA;
			end if;
		end if;
	end process;
end RTL;