ipir.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;

entity IPIR is
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_RDIP     :  in std_logic;
          I_RDIR     :  in std_logic;
          I_WRIP     :  in std_logic;
          I_WRIR     :  in std_logic;
          I_DATA     :  in std_logic_vector(15 downto 0 );
          I_EARQ     :  in std_logic;
          O_IPF      : out std_logic;
          O_IRDATA   : out std_logic_vector(15 downto 0 );
          O_IPIRDATA : out std_logic_vector(15 downto 0 )
          );
end IPIR;
 
architecture RTL of IPIR is
 
signal IP_IPF : std_logic;
signal IP_IP  : std_logic_vector(15 downto 0 );
signal IR_IR  : std_logic_vector(15 downto 0 );

component IP
    port( I_CLK    :  in std_logic;
		  I_RST    :  in std_logic;
		  I_RDIP   :  in std_logic; --READ signal 
		  I_WRIP   :  in std_logic;
	      I_DATA   :  in std_logic_vector(15 downto 0); --input data
		  O_IPF    : out std_logic; --address out => '1'
		  O_IPDATA : out std_logic_vector(15 downto 0) --output data
		  );
end component;

component IR
    Port( I_CLK    :  in std_logic;
          I_RST    :  in std_logic;
		  I_WRIR   :  in std_logic; --write signal from EUC  
		  I_EARQ   :  in std_logic;--EA out => '1' 
		  I_DATA   :  in std_logic_vector(15 downto 0); 
          O_IRDATA : out std_logic_vector(15 downto 0)
		  ); 
end component;

component IPIRMPX
    port( I_CLK      :  in std_logic;
		  I_RST      :  in std_logic;
		  I_IPDATA   :  in std_logic_vector(15 downto 0); --input data from IP
          I_IRDATA   :  in std_logic_vector(15 downto 0); --input data from IR
          I_IPF      :  in std_logic; --address out from IP signal
          I_IRF      :  in std_logic; --address out from IR signal
		  O_IPIRDATA : out std_logic_vector(15 downto 0)  --output to ADD
		  );
end component; 

begin
	IP_IPIR : IP
    port map ( 
		I_CLK => I_CLK,
		I_RST => I_RST,
		I_RDIP => I_RDIP,
		I_WRIP => I_WRIP,
	    I_DATA => I_DATA,
		O_IPF => IP_IPF,
		O_IPDATA => IP_IP
		);

	IR_IPIR : IR
    port map ( 
		I_CLK => I_CLK,
        I_RST => I_RST,
		I_WRIR => I_WRIR,
		I_EARQ => I_EARQ,
		I_DATA => I_DATA,
        O_IRDATA => IR_IR
		); 

	IPIRMPX_IPIR : IPIRMPX
    port map ( 
		I_CLK => I_CLK,
		I_RST => I_RST,
		I_IPDATA => IP_IP,
        I_IRDATA => IR_IR,
        I_IPF => IP_IPF,
        I_IRF => I_RDIR,
		O_IPIRDATA => O_IPIRDATA
		);

	O_IPF <= IP_IPF; 
	O_IRDATA  <= IR_IR;

end RTL;