divcount.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.ALL;

entity DIVCOUNT is
    port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_BW       :  in std_logic;
		  I_SCOUNT	 :  in std_logic;
		  O_DIVCOUNT : out std_logic_vector( 4 downto 0);
          O_LOOPEND  : out std_logic
		  );
end DIVCOUNT;

architecture RTL of DIVCOUNT is

signal count   : std_logic_vector(4 downto 0);
signal loopend : std_logic;

begin

	O_DIVCOUNT <= count;
	O_LOOPEND  <= loopend;

	divcount_reg : 
	process	(I_CLK,I_RST,I_BW,I_SCOUNT,count) 
	begin
		if (I_RST = RST_ACT)then
			count <= "00000";
		elsif(I_CLK'event and I_CLK = '0')then
			if(I_SCOUNT = '1')then
				if (I_BW = '0') then
					if(count = "01111")then
						count <= "00000";
					else
						count <= count + "00001";
					end if;
				else
					if(count = "11111")then
						count <= "00000";
					else
						count <= count + "00001";
					end if;
				end if;
			end if;
		end if;
	end process;

	loopend_reg :
	process	(I_CLK,I_RST,I_BW,I_SCOUNT,count) 
	begin
		if (I_RST = RST_ACT) then
			loopend <= '0';
		elsif (I_CLK'event and I_CLK = '0') then
			if(I_SCOUNT = '1')then
				if (I_BW = '0')then
					if(count = "01111")then
						loopend <= '1';
					else
						loopend <= '0';
					end if;
				else
					if(count = "11111")then
						loopend <= '1';
					else
						loopend <= '0';
					end if;
				end if;
			end if;
		end if;
	end process;

end RTL;