cfe.vhd

X8086的VHDL源码

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--   FILE NAME : C_FE_REG.vhd
--   FUNCTION  : Control FETCH Unit,read register
--   AUTHOR    : Kazuma Mishima
--   DATE      : 6/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;

entity CFE is
    port( I_CLK    :  in std_logic;
		  I_RST    :  in std_logic;
	      I_ENDRC  :  in std_logic; --end read cycle  => '1'
	 	  I_ENDWC  :  in std_logic; --end write cycle => '1'
	      I_FE     :  in std_logic; --fetch signal             
		  I_WRQUE  :  in std_logic; --write QUE => '1'
          I_RD     :  in std_logic; --read signal from EU
          I_WR     :  in std_logic; --write signal from EU
		  I_RDSR   :  in std_logic; --SR read signal
          I_WRSR   :  in std_logic; --write SR signal
		  I_WRIP   :  in std_logic; --write IP signal
		  I_WRIR   :  in std_logic; --write IR signal
		  I_EUCRST :  in std_logic; --from EUC reset signal
		  I_NFE    :  in std_logic; --from EUC not fetch signal
		  I_HLT    :  in std_logic; --HLT signal
		  O_NOP_V  : out std_logic;    
 		  O_RDSR   : out std_logic; --register read signal
          O_RDIP   : out std_logic; --IP register read signal(fetch)
		  O_RDIR   : out std_logic  --IR register read signal
		  );
end CFE;

architecture RTL of CFE is

signal nop : std_logic; --not operation

begin

	O_NOP_V <= nop;

--read register signal
	process(I_CLK,I_RST,I_NFE,I_HLT,nop,I_RDSR,I_RD,I_WR,I_FE,I_WRSR,I_WRIR,I_WRIP)
	begin
		if (I_RST = RST_ACT) then
			O_RDSR <= '0';
			O_RDIP <= '0';
			O_RDIR <= '0';
		elsif (I_CLK'event and I_CLK='0') then
	 		--fetch
			if (((I_NFE='0' and I_HLT='0') 
			 and (nop='1' and I_RDSR='0')) 
			 and (I_RD='0' and I_WR='0' and I_FE='1')              
		     and (I_WRSR= '0' and  I_WRIR='0' and I_WRIP='0'))then   --not write SR,IP,IR 
				O_RDSR <= '0';
				O_RDIP <= '1';
				O_RDIR <= '0';
		--read mem or write mem or read segment register
			elsif ((I_RD='1' or I_WR='1' or I_RDSR='1') and (nop='1' and I_HLT='0'))then        
				O_RDSR <= '1';
				O_RDIP <= '0';
				O_RDIR <= '1';
			else	   
				O_RDSR <= '0';
				O_RDIP <= '0';
				O_RDIR <= '0';
			end if;
		end if;
	end process;

--not read,write,fetch signal
	process(I_CLK,I_RST,I_WRQUE,I_ENDRC,I_ENDWC,I_EUCRST,I_NFE,I_HLT,nop,I_RDSR,I_RD,I_WR,I_FE,I_WRSR,I_WRIR,I_WRIP)
	begin
		if (I_RST = RST_ACT) then
			nop <= '1';
		elsif (I_CLK'event and I_CLK='0') then
			if   ((I_WRQUE = '1' or I_ENDRC = '1') or (I_ENDWC = '1' or I_EUCRST='1'))then --end fetch(write Q),end read,end write,
				nop <= '1';
			elsif(((I_NFE='0' and I_HLT='0') and (nop='1' and I_RDSR='0')) and (I_RD='0' and I_WR='0' and I_FE='1')              
		          and (I_WRSR= '0' and  I_WRIR='0' and I_WRIP='0'))then --not write SR,IP,IR 
				nop <= '0';
			elsif((I_RD='1' or I_WR='1' or I_WRSR='1') and (nop='1' and I_HLT='0'))then
				nop <= '0';
			end if;
		end if;
	end process;

end RTL;