mpx2in1out.vhd

X8086的VHDL源码

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--   FILE NAME : EU_M_MPX_BIU.vhd
--   FUNCTION  : select DATA (from Segment REGISTAR or from EU or IR)
--   AUTHOR    : Kazuma Mishima
--   DATE      : 10/2001
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MPX2IN1OUT is
	generic( WID : integer := 16 
			 ); 
    port( I_SW     :  in std_logic;
          I_DATA0  :  in std_logic_vector( WID-1 downto 0);
          I_DATA1  :  in std_logic_vector( WID-1 downto 0);
          O_DATA   : out std_logic_vector( WID-1 downto 0)
		  );
end MPX2IN1OUT ;

architecture RTL of MPX2IN1OUT is

begin
	process(I_SW,I_DATA0,I_DATA1)
	begin
		if (I_SW = '1') then
			O_DATA <= I_DATA1;
		else
			O_DATA <= I_DATA0;
		end if;
	end process;
end RTL;