eafsm.vhd

X8086的VHDL源码

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--  
--      VHDL code generated by Visual HDL
--
--  Design Unit:
--  ------------
--      Unit    Name  :  EA_FSM_EACU
--      Library Name  :  eu
--  
--      Creation Date :  Sat Feb 02 05:53:45 2002
--      Version       :  6.7.0.patch1-pc build 20 from Feb 20 2001
--  
--  Options Used:
--  -------------
--      Target
--         HDL        :  VHDL
--         Purpose    :  Synthesis
--         Vendor     :  Leonardo
--  
--      Style
--         Use Procedures                 :  No
--         Code Destination               :  Combined file
--         Attach Packages                :  No
--         Generate Entity                :  Yes
--         Attach Directives              :  Yes
--         Structural                     :  No
--         Configuration Specification    :  No
--         library name in
--         Configuration Specification    :  No
--         Configuration Declaration      :  None
--         IF for state selection         :  No
--         Preserve spacing for free text :  Yes
--         Sort Ports by mode             :  No
--         Declaration alignment          :  No
--
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----------------------------------------------------
--  
--  Library Name :  eu
--  Unit    Name :  EA_FSM_EACU
--  Unit    Type :  State Machine
--  
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library ieee;
use ieee.STD_LOGIC_1164.all;
use WORK.UPAC.ALL;

entity EAFSM is
	port( I_CLK       :  in std_logic;
          I_RST       :  in std_logic;
          I_QUEEMPTY  :  in std_logic;
          I_BW        :  in std_logic;
          I_EA        :  in std_logic;
          I_RM        :  in std_logic_vector( 2 downto 0 );
          I_MOD       :  in std_logic_vector( 1 downto 0 );
          O_EACUSTATE : out std_logic_vector( 2 downto 0 )
          );
end EAFSM;
 
architecture RTL of EAFSM is
 
constant INITIAL  : std_logic_vector(2 downto 0 ) := "000";
constant D16      : std_logic_vector(2 downto 0 ) := "001";
constant ALU_OUT  : std_logic_vector(2 downto 0 ) := "010";
constant DATA1    : std_logic_vector(2 downto 0 ) := "011";
constant DATA2    : std_logic_vector(2 downto 0 ) := "100";
constant DATA3    : std_logic_vector(2 downto 0 ) := "101";
constant DATA_OUT : std_logic_vector(2 downto 0 ) := "110";
constant TMP_DATA : std_logic_vector(2 downto 0 ) := "111";

signal currentstate : std_logic_vector(2 downto 0 ); 
signal eacustate    : std_logic_vector(2 downto 0 );
  
begin

	O_EACUSTATE <= currentstate;

	CURRENT_STATE : 
	process(I_RST,I_CLK,eacustate)
	begin
		if (I_RST = RST_ACT ) then
			currentstate <= INITIAL;
		elsif (I_CLK'event and I_CLK = '0') then
			currentstate <= eacustate;
		end if;
	end process;

-- Synchronous process
	EACU_FSM:
	process (currentstate,I_EA,I_QUEEMPTY,I_MOD,I_RM,I_BW)
	begin
		case currentstate is
		when INITIAL =>
			if    (I_EA = '0' or  I_QUEEMPTY = '1') then
				eacustate <= INITIAL;
			elsif (I_MOD = "01" 
			   or  I_MOD = "10" 
			   or (I_MOD = "00" and I_RM(2) = '0')
			   or (I_MOD = "00" and I_RM = "110")) then
				eacustate <= DATA1;
			elsif (I_MOD = "00" and (I_RM = "100" 
								  or I_RM = "101" 
								  or I_RM = "111")) then
				eacustate <= DATA_OUT;
			else
				eacustate <= INITIAL;
			end if;
		when D16 =>
			if   ((I_MOD = "00" and I_RM = "110" and I_BW = '1') 
			   or (I_MOD = "10" and I_RM(2) = '1')) then
				eacustate <= ALU_OUT;
			elsif (I_MOD = "10" and I_RM(2) = '0') then
				eacustate <= TMP_DATA;
			else
				eacustate <= D16;
			end if;
		when ALU_OUT =>
			eacustate <= INITIAL;
		when DATA1 =>
			eacustate <= DATA2;
		when DATA2 =>
			if     (I_MOD = "10" or 
				   (I_MOD = "00" and I_RM = "110" and I_BW = '1')) then
				eacustate <= D16;
			elsif  (I_MOD = "01" and I_RM(2) = '0') then
				eacustate <= TMP_DATA;
			elsif ((I_MOD = "00" and I_RM(2) = '0') 
				or (I_MOD = "01" and I_RM(2) = '1') 
			    or (I_MOD = "00" and I_RM = "110" and I_BW = '0')) then
				eacustate <= ALU_OUT;
			else
				eacustate <= DATA2;
			end if;
		when DATA3 =>
			eacustate <= ALU_OUT;
		when DATA_OUT =>
			eacustate <= INITIAL;
		when TMP_DATA =>
			eacustate <= DATA3;
		when others =>
			eacustate <= INITIAL;
		end case;
	end process;

end RTL;