mp8086.vhd

X8086的VHDL源码

	      I_A19A16  :  in std_logic_vector( 3 downto 0 ); --address 19bit~16bit
		  I_EXTBUS  :  in std_logic_vector(15 downto 0 );
          I_WR_N    :  in std_logic; --when write => 'L'
          I_RD_N    :  in std_logic; --when read => 'L'           
          I_BHE     :  in std_logic; --from DC BHE signal
		  I_DATAH   :  in std_logic_vector( 7 downto 0 ); --from memory DATA High
          I_DATAL   :  in std_logic_vector( 7 downto 0 ); --from memory DATA Low
		  O_WRH     : out std_logic; --High memory write signal (write => '1')
		  O_WRL     : out std_logic; --Low memory write signal (write => '1')
          O_DATAH   : out std_logic_vector( 7 downto 0 ); --write memory data High
          O_DATAL   : out std_logic_vector( 7 downto 0 ); --write memory data Low
          O_ADR     : out std_logic_vector(MADRWIDTH-1 downto 0 ); --memory address
		  O_EXTBUS  : out std_logic_vector(15 downto 0 )
		  );  
end component;
 
component Hmem
	port( data	    :  in std_logic_vector ( 7 downto 0);
		  wraddress	:  in std_logic_vector ( 7 downto 0);
		  rdaddress	:  in std_logic_vector ( 7 downto 0);
		  wren		:  in std_logic := '1';
		  clock		:  in std_logic ;
		  q		    : out std_logic_vector ( 7 downto 0)
	      );
end component;

component Lmem
	port( data	    :  in std_logic_vector ( 7 downto 0);
		  wraddress	:  in std_logic_vector ( 7 downto 0);
		  rdaddress	:  in std_logic_vector ( 7 downto 0);
		  wren		:  in std_logic := '1';
		  clock		:  in std_logic ;
		  q		    : out std_logic_vector ( 7 downto 0)
	      );
end component;

component CONV7SEG
    port( I_DATA1          :  in std_logic_vector(15 downto 0);
          I_DATA2          :  in std_logic_vector(15 downto 0);
          O_7SEGDATA1 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA2 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA3 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA4 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA5 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA6 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA7 : out std_logic_vector( 7 downto 0);
          O_7SEGDATA8 : out std_logic_vector( 7 downto 0)
		  );
end component;

begin
	T_BIU_MP8086 : BIU
	port map ( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_RDY => I_RDY,
        I_MOD => EUC_MOD,
        I_BW => EUC_BW,
        I_RM => EUC_RM,
        I_CSR => EUC_CTRLSRSEL,
        I_SRSEL => EUC_SRSEL,
        I_EUDATA => EUINBUS_DATA2BIU,
        I_EARQ => STDEC_EARQ,
        I_RDQUE => CSSEL_RDQUE,
        I_RD => EUC_RD,
        I_WR => EUC_WR,
        I_WRIP => EUC_WRIP,
        I_WRSR => EUC_WRSR,
        I_EAPLUS2 => EUC_EAPLUS2,
        I_2SR => EUC_EUC2SR,
        I_OADR => EUC_ADR16,
        I_ADROUT => EUC_ADROUT,
        I_EUCDATA => EUC_DATA,
        I_HLT => EUC_HLT,
        I_IO => EUC_IO,
        I_MDTF => EUC_MDTF,
        I_NFE => EUC_NFE,
        I_PLUSMOD => EUC_PLUSMOD,
        I_PLUSOP => EUC_PLUSOP, 
        I_QUERST => EUC_QUERST,
        I_RDIR => EUC_RDIR,
        I_EUCRST => EUC_RST,
        I_2BIU => EUC_EUC2BIU,
        I_2EU => EUC_EUC2EU,
        I_ORPCSR => EUC_ORP,
        I_ORPSRSEL => EUC_SRSELORP,
        I_RDSR => EUC_RDSR,
        I_WRIR => EUC_WRIR,
        I_WRPLUS => EUC_WRPLUS,
        I_EXTBUS => MCU_EXTBUS,
        O_CS_V => O_CS_V,
        O_DS_V => O_DS_V,
        O_ES_V => O_ES_V,
        O_SS_V => O_SS_V,
        O_BCUSTATE_V => O_BCUSTATE_V,
		O_DCSTATE_V => O_DCSTATE_V,
        O_DEN_N => O_DEN_N,
        O_DTR => O_DTR,
        O_QUEEMPTY => FIFO_QUEEMPTY,
        O_QUEFULL => O_QUEFULL,
		O_ALE => BCU_ALE,
        O_BHE => DC_BHE,
        O_NOP_V => O_NOP_V,
        O_A19A16 => BCU_A19A16,
        O_EXTBUS => BCU_EXTBUS,
        O_ENDRC => DC_RCF,
        O_ENDWC => DC_WCF,
        O_IO => O_IO,
        O_BDATA => FIFO_BDATA,
        O_BIUDATA => EUSRMPX_DATA,
        O_NEXTIP => NEXTIP_DATA,
        O_RD_N => BCU_RD_N,
        O_WR_N => BCU_WR_N
		);

	T_CUEU_MP8086 : CUEU
	port map ( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_S77 => I_S77,
        I_QUEEMPTY => FIFO_QUEEMPTY,  
        I_ENDRC => DC_RCF,
        I_ENDWC => DC_WCF,
        I_BDATA => FIFO_BDATA,
        I_BIUDATA => EUSRMPX_DATA,
        I_NEXTIP => NEXTIP_DATA,
        O_EUCRST => EUC_RST,
        O_QUERST => EUC_QUERST,
        O_BW => EUC_BW,
        O_MOD => EUC_MOD,
        O_RM => EUC_RM,
        O_RDSR => EUC_RDSR,
        O_WRSR => EUC_WRSR,
        O_WRIP => EUC_WRIP,
        O_RDIR => EUC_RDIR,
        O_WRIR => EUC_WRIR,
        O_RD => EUC_RD,
        O_WR => EUC_WR,
        O_ADROUT => EUC_ADROUT,
        O_IO => EUC_IO,
        O_MDTF => EUC_MDTF,
        O_NFE => EUC_NFE,
        O_WRPLUS => EUC_WRPLUS,
        O_EAPLUS2 => EUC_EAPLUS2,
        O_2BIU => EUC_EUC2BIU,
        O_2EU => EUC_EUC2EU,
        O_2SR => EUC_EUC2SR,
        O_HLT => EUC_HLT,
        O_CSR => EUC_CTRLSRSEL,
        O_SRSEL => EUC_SRSEL,
        O_ORPCSR => EUC_ORP,
        O_ORPSRSEL => EUC_SRSELORP,
        O_RDQUE => CSSEL_RDQUE,
        O_EARQ => STDEC_EARQ,
        O_TYPEZERO => O_TYPEZERO,
        O_PLUSMOD => EUC_PLUSMOD,
        O_PLUSOP => EUC_PLUSOP,
        O_EUDATA => EUINBUS_DATA2BIU,
        O_EUCDATA => EUC_DATA,
        O_OADR => EUC_ADR16,
		O_OP_V => O_OP_V,
        O_EUCSTATE_V => O_EUCSTATE_V,
        O_DIVSTATE => O_DIVSTATE,
        O_EACUSTATE => O_EACUSTATE,
        O_FREG => O_FREG,
		O_ALUDATA_V => O_ALUDATA_V,
        O_REG1 => O_REG1,
        O_REG2 => O_REG2,
        O_AX_V => GRU_AX,
        O_BP_V => O_BP_V,
        O_BX_V => O_BX_V,
        O_CX_V => GRU_CX,
        O_DI_V => O_DI_V,
        O_DX_V => O_DX_V,
        O_SI_V => O_SI_V,
        O_SP_V => O_SP_V
		); 

 	MCU_MP8086 : MCU
	generic map( 
		MADRWIDTH => 8
		)
    port map ( 
		I_CLK => I_CLK,
		I_RST => I_RST,
		I_ALE => BCU_ALE,
	    I_A19A16 => BCU_A19A16,
		I_EXTBUS => BCU_EXTBUS,
        I_WR_N => BCU_WR_N,
        I_RD_N => BCU_RD_N,
        I_BHE => DC_BHE,
		I_DATAH => HMEM_Q,
        I_DATAL => LMEM_Q,
		O_WRH => MCU_WRH,
		O_WRL => MCU_WRL,
        O_DATAH => MCU_DATAH,
        O_DATAL => MCU_DATAL,
        O_ADR => MCU_ADR,
		O_EXTBUS => MCU_EXTBUS
		);  

	HMEM_MP8086 : Hmem
	port map( 
		data => MCU_DATAH,
		wraddress => MCU_ADR,
	 	rdaddress => MCU_ADR,
		wren => MCU_WRH,
		clock => I_CLK,
		q => HMEM_Q
	    );

    LMEM_MP8086 : Lmem
	port map( 
		data => MCU_DATAL,
		wraddress => MCU_ADR,
		rdaddress => MCU_ADR,
		wren => MCU_WRL,
		clock => I_CLK,
		q => LMEM_Q
	    );

	CONV7SEG_MP8086 : CONV7SEG
    port map( 
		I_DATA1 => GRU_AX,
        I_DATA2 => GRU_CX,
        O_7SEGDATA1 => O_7SEGDATA1,
        O_7SEGDATA2 => O_7SEGDATA2,
        O_7SEGDATA3 => O_7SEGDATA3,
        O_7SEGDATA4 => O_7SEGDATA4,
        O_7SEGDATA5 => O_7SEGDATA5,
        O_7SEGDATA6 => O_7SEGDATA6,
        O_7SEGDATA7 => O_7SEGDATA7,
        O_7SEGDATA8 => O_7SEGDATA8
		);

	O_BDATA       <= FIFO_BDATA;
	O_RM          <= EUC_RM;
	O_MOD         <= EUC_MOD;
	O_MCUEXTBUS_V <= MCU_EXTBUS; 
	O_BCUEXTBUS_V <= BCU_EXTBUS;
	O_WRH_V       <= MCU_WRH;
	O_WRL_V       <= MCU_WRL; 
	O_DATAH_V     <= MCU_DATAH;
	O_DATAL_V     <= MCU_DATAL;
	O_ADR_V       <= MCU_ADR;
	O_EARQ        <= STDEC_EARQ;
    O_AX_V        <= GRU_AX;
    O_CX_V        <= GRU_CX;

end RTL;