mp8086.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity MP8086 is
	port( I_CLK         :  in std_logic;
          I_RST         :  in std_logic;
          I_RDY         :  in std_logic;
          I_S77         :  in std_logic;
		  O_ALUDATA_V   : out std_logic_vector(15 downto 0 );
          O_AX_V        : out std_logic_vector(15 downto 0 );
          O_CX_V        : out std_logic_vector(15 downto 0 );
          O_BX_V        : out std_logic_vector(15 downto 0 );
          O_DX_V        : out std_logic_vector(15 downto 0 );
          O_SP_V        : out std_logic_vector(15 downto 0 );
          O_BP_V        : out std_logic_vector(15 downto 0 );
          O_SI_V        : out std_logic_vector(15 downto 0 );
          O_DI_V        : out std_logic_vector(15 downto 0 );
          O_EUCSTATE_V  : out std_logic_vector( 8 downto 0 );
          O_BCUSTATE_V  : out std_logic_vector( 2 downto 0 );
          O_EACUSTATE   : out std_logic_vector( 2 downto 0 );
          O_DIVSTATE    : out std_logic_vector( 3 downto 0 );
		  O_DCSTATE_V   : out std_logic_vector( 3 downto 0 );
          O_FREG        : out std_logic_vector( 8 downto 0 );
          O_DS_V        : out std_logic_vector(15 downto 0 );
          O_ES_V        : out std_logic_vector(15 downto 0 );
          O_SS_V        : out std_logic_vector(15 downto 0 );
          O_CS_V        : out std_logic_vector(15 downto 0 );
		  O_MOD         : out std_logic_vector( 1 downto 0 );
          O_RM          : out std_logic_vector( 2 downto 0 );
          O_QUEFULL     : out std_logic;
          O_DEN_N       : out std_logic;
          O_DTR         : out std_logic;
          O_NOP_V       : out std_logic;
          O_IO          : out std_logic;
          O_TYPEZERO    : out std_logic;
		  O_EARQ        : out std_logic;
          O_BDATA       : out std_logic_vector( 7 downto 0 );
          O_ADR_V       : out std_logic_vector( 7 downto 0 );
		  O_BCUEXTBUS_V : out std_logic_vector(15 downto 0 );
          O_MCUEXTBUS_V : out std_logic_vector(15 downto 0 );
          O_DATAH_V     : out std_logic_vector( 7 downto 0 );
          O_DATAL_V     : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA1   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA2   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA3   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA4   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA5   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA6   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA7   : out std_logic_vector( 7 downto 0 );
          O_7SEGDATA8   : out std_logic_vector( 7 downto 0 );
          O_WRH_V       : out std_logic;
          O_WRL_V       : out std_logic;
		  O_OP_V        : out std_logic_vector( 7 downto 0 );
          O_REG1        : out std_logic_vector(15 downto 0 );
          O_REG2        : out std_logic_vector(15 downto 0 )
		  );
end MP8086;
 
architecture RTL of MP8086 is
 
signal BCU_ALE          : std_logic;
signal DC_BHE           : std_logic;
signal FIFO_QUEEMPTY    : std_logic;
signal BCU_EXTBUS       : std_logic_vector(15 downto 0 );
signal FIFO_BDATA       : std_logic_vector( 7 downto 0 );
signal DC_RCF           : std_logic;
signal DC_WCF           : std_logic;
signal EUC_BW           : std_logic;
signal EUC_MOD          : std_logic_vector( 1 downto 0 );
signal EUC_RD           : std_logic;
signal EUC_RM           : std_logic_vector( 2 downto 0 );
signal STDEC_EARQ       : std_logic;
signal BCU_RD_N         : std_logic;
signal BCU_WR_N         : std_logic;
signal EUC_WRIP         : std_logic;
signal EUC_WRSR         : std_logic;
signal EUC_HLT          : std_logic;
signal EUC_IO           : std_logic;
signal EUC_NFE          : std_logic;
signal EUC_QUERST       : std_logic;
signal EUC_RST          : std_logic;
signal EUC_RDSR         : std_logic;
signal EUC_WRIR         : std_logic;
signal MCU_EXTBUS       : std_logic_vector(15 downto 0 );
signal NEXTIP_DATA      : std_logic_vector(15 downto 0 );
signal BCU_A19A16       : std_logic_vector( 3 downto 0 );
signal CSSEL_RDQUE      : std_logic;
signal EUINBUS_DATA2BIU : std_logic_vector(15 downto 0 );
signal EUC_EAPLUS2      : std_logic;
signal EUC_EUC2SR       : std_logic;
signal EUC_ADR16        : std_logic_vector(15 downto 0 );
signal EUC_ADROUT       : std_logic;
signal EUC_CTRLSRSEL    : std_logic;
signal EUC_DATA         : std_logic_vector(15 downto 0 );
signal EUC_MDTF         : std_logic;
signal EUC_PLUSMOD      : std_logic_vector( 1 downto 0 );
signal EUC_PLUSOP       : std_logic_vector( 2 downto 0 );
signal EUC_RDIR         : std_logic;
signal EUC_EUC2BIU      : std_logic;
signal EUC_EUC2EU       : std_logic;
signal EUC_ORP          : std_logic;
signal EUC_SRSELORP     : std_logic_vector( 1 downto 0 );
signal EUC_SRSEL        : std_logic_vector( 1 downto 0 );
signal EUC_WRPLUS       : std_logic;
signal EUC_WR           : std_logic;
signal MCU_ADR          : std_logic_vector( 7 downto 0 );
signal MCU_DATAH        : std_logic_vector( 7 downto 0 );
signal MCU_DATAL        : std_logic_vector( 7 downto 0 );
signal MCU_WRH          : std_logic;
signal MCU_WRL          : std_logic;
signal EUSRMPX_DATA     : std_logic_vector(15 downto 0 );
signal HMEM_Q           : std_logic_vector( 7 downto 0 );
signal LMEM_Q           : std_logic_vector( 7 downto 0 );
signal GRU_AX           : std_logic_vector(15 downto 0 ); 
signal GRU_CX           : std_logic_vector(15 downto 0 ); 

component BIU
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;
          I_RDY        :  in std_logic;
          I_MOD        :  in std_logic_vector( 1 downto 0 );
          I_BW         :  in std_logic;
          I_RM         :  in std_logic_vector( 2 downto 0 );
          I_CSR        :  in std_logic;
          I_SRSEL      :  in std_logic_vector( 1 downto 0 );
          I_EUDATA     :  in std_logic_vector(15 downto 0 );
          I_EARQ       :  in std_logic;
          I_RDQUE      :  in std_logic;
          I_RD         :  in std_logic;
          I_WR         :  in std_logic;
          I_WRIP       :  in std_logic;
          I_WRSR       :  in std_logic;
          I_EAPLUS2    :  in std_logic;
          I_2SR        :  in std_logic;
          I_OADR       :  in std_logic_vector(15 downto 0 );
          I_ADROUT     :  in std_logic;
          I_EUCDATA    :  in std_logic_vector(15 downto 0 );
          I_HLT        :  in std_logic;
          I_IO         :  in std_logic;
          I_MDTF       :  in std_logic;
          I_NFE        :  in std_logic;
          I_PLUSMOD    :  in std_logic_vector( 1 downto 0 );
          I_PLUSOP     :  in std_logic_vector( 2 downto 0 );
          I_QUERST     :  in std_logic;
          I_RDIR       :  in std_logic;
          I_EUCRST     :  in std_logic;
          I_2BIU       :  in std_logic;
          I_2EU        :  in std_logic;
          I_ORPCSR     :  in std_logic;
          I_ORPSRSEL   :  in std_logic_vector( 1 downto 0 );
          I_RDSR       :  in std_logic;
          I_WRIR       :  in std_logic;
          I_WRPLUS     :  in std_logic;
          I_EXTBUS     :  in std_logic_vector(15 downto 0 );
          O_CS_V       : out std_logic_vector(15 downto 0 );
          O_DS_V       : out std_logic_vector(15 downto 0 );
          O_ES_V       : out std_logic_vector(15 downto 0 );
          O_SS_V       : out std_logic_vector(15 downto 0 );
          O_BCUSTATE_V : out std_logic_vector( 2 downto 0 );
		  O_DCSTATE_V  : out std_logic_vector( 3 downto 0 );
          O_DEN_N      : out std_logic;
          O_DTR        : out std_logic;
          O_QUEEMPTY   : out std_logic;
          O_QUEFULL    : out std_logic;
		  O_ALE        : out std_logic;
          O_BHE        : out std_logic;
          O_NOP_V      : out std_logic;
          O_A19A16     : out std_logic_vector( 3 downto 0 );
          O_EXTBUS     : out std_logic_vector(15 downto 0 );
          O_ENDRC      : out std_logic;
          O_ENDWC      : out std_logic;
          O_IO         : out std_logic;
          O_BDATA      : out std_logic_vector( 7 downto 0 );
          O_BIUDATA    : out std_logic_vector(15 downto 0 );
          O_NEXTIP     : out std_logic_vector(15 downto 0 );
          O_RD_N       : out std_logic;
          O_WR_N       : out std_logic 
		  );
end component;

component CUEU
	port( I_CLK        :  in std_logic;
          I_RST        :  in std_logic;
          I_S77        :  in std_logic;
          I_QUEEMPTY   :  in std_logic;
          I_ENDRC      :  in std_logic;
          I_ENDWC      :  in std_logic;
          I_BDATA      :  in std_logic_vector( 7 downto 0 );
          I_BIUDATA    :  in std_logic_vector(15 downto 0 );
          I_NEXTIP     :  in std_logic_vector(15 downto 0 );
          O_EUCRST     : out std_logic;
          O_QUERST     : out std_logic;
          O_BW         : out std_logic;
          O_MOD        : out std_logic_vector( 1 downto 0 );
          O_RM         : out std_logic_vector( 2 downto 0 );
          O_RDSR       : out std_logic;
          O_WRSR       : out std_logic;
          O_WRIP       : out std_logic;
          O_RDIR       : out std_logic;
          O_WRIR       : out std_logic;
          O_RD         : out std_logic;
          O_WR         : out std_logic;
          O_ADROUT     : out std_logic;
          O_IO         : out std_logic;
          O_MDTF       : out std_logic;
          O_NFE        : out std_logic;
          O_WRPLUS     : out std_logic;
          O_EAPLUS2    : out std_logic;
          O_2BIU       : out std_logic;
          O_2EU        : out std_logic;
          O_2SR        : out std_logic;
          O_HLT        : out std_logic;
          O_CSR        : out std_logic;
          O_SRSEL      : out std_logic_vector( 1 downto 0 );
          O_ORPCSR     : out std_logic;
          O_ORPSRSEL   : out std_logic_vector( 1 downto 0 );
          O_RDQUE      : out std_logic;
          O_EARQ       : out std_logic;
          O_TYPEZERO   : out std_logic;
          O_PLUSMOD    : out std_logic_vector( 1 downto 0 );
          O_PLUSOP     : out std_logic_vector( 2 downto 0 );
          O_EUDATA     : out std_logic_vector(15 downto 0 );
          O_EUCDATA    : out std_logic_vector(15 downto 0 );
          O_OADR       : out std_logic_vector(15 downto 0 );
		  O_OP_V       : out std_logic_vector( 7 downto 0 );
          O_EUCSTATE_V : out std_logic_vector( 8 downto 0 );
          O_DIVSTATE   : out std_logic_vector( 3 downto 0 );
          O_EACUSTATE  : out std_logic_vector( 2 downto 0 );
          O_FREG       : out std_logic_vector( 8 downto 0 );
		  O_ALUDATA_V  : out std_logic_vector(15 downto 0 );
          O_REG1       : out std_logic_vector(15 downto 0 );
          O_REG2       : out std_logic_vector(15 downto 0 );
          O_AX_V       : out std_logic_vector(15 downto 0 );
          O_BP_V       : out std_logic_vector(15 downto 0 );
          O_BX_V       : out std_logic_vector(15 downto 0 );
          O_CX_V       : out std_logic_vector(15 downto 0 );
          O_DI_V       : out std_logic_vector(15 downto 0 );
          O_DX_V       : out std_logic_vector(15 downto 0 );
          O_SI_V       : out std_logic_vector(15 downto 0 );
          O_SP_V       : out std_logic_vector(15 downto 0 )        
		  ); 
end component;

component MCU
	generic( MADRWIDTH : integer  --memory WORD
			 ); 
    Port( I_CLK     :  in std_logic;
		  I_RST     :  in std_logic;
		  I_ALE     :  in std_logic; --address latch signal