srir.vhd

X8086的VHDL源码

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library synplify;
use synplify.attributes.all;
  
entity SRIR is
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_MOD      :  in std_logic_vector( 1 downto 0 );
          I_RM       :  in std_logic_vector( 2 downto 0 );
          I_NFE      :  in std_logic;
          I_RD       :  in std_logic;
          I_WR       :  in std_logic;
          I_WRIP     :  in std_logic;
          I_WRIR     :  in std_logic;
          I_RDSR     :  in std_logic;
          I_WRSR     :  in std_logic;
          I_WRPLUS   :  in std_logic;
          I_HLT      :  in std_logic;
          I_MDTF     :  in std_logic;
          I_PLUSMOD  :  in std_logic_vector( 1 downto 0 );
          I_PLUSOP   :  in std_logic_vector( 2 downto 0 );
          I_EUCRST   :  in std_logic;
          I_CSR      :  in std_logic;
          I_ORPCSR   :  in std_logic;
          I_SRSEL    :  in std_logic_vector( 1 downto 0 );
          I_ORPSRSEL :  in std_logic_vector( 1 downto 0 );
          I_EARQ     :  in std_logic;
          I_WRQUE    :  in std_logic;
          I_FE       :  in std_logic;
          I_ENDRC    :  in std_logic;
          I_ENDWC    :  in std_logic;
          I_EUDATA   :  in std_logic_vector(15 downto 0 );
          I_BIUDATA  :  in std_logic_vector(15 downto 0 );
          O_NOP_V    : out std_logic;
          O_IPF      : out std_logic;
          O_IRF      : out std_logic;
          O_IRDATA   : out std_logic_vector(15 downto 0 );
          O_IPIRDATA : out std_logic_vector(15 downto 0 );
          O_NEXTIP   : out std_logic_vector(15 downto 0 );
          O_SREGDATA : out std_logic_vector(15 downto 0 );
          O_CS_V     : out std_logic_vector(15 downto 0 );
          O_DS_V     : out std_logic_vector(15 downto 0 );
          O_ES_V     : out std_logic_vector(15 downto 0 );
          O_SS_V     : out std_logic_vector(15 downto 0 )
		  ); 
end SRIR;
  
use work.all;
architecture RTL of SRIR is
 
signal EUMMPX_DATA : std_logic_vector(15 downto 0 );
signal CFE_RDSR    : std_logic;
signal CFE_RDIP    : std_logic;
signal CFE_RDIR    : std_logic;
signal CSEG_SRSEL  : std_logic_vector( 1 downto 0 );

component IPIR
	port( I_CLK      :  in std_logic;
          I_RST      :  in std_logic;
          I_RDIP     :  in std_logic;
          I_RDIR     :  in std_logic;
          I_WRIP     :  in std_logic;
          I_WRIR     :  in std_logic;
          I_DATA     :  in std_logic_vector(15 downto 0 );
          I_EARQ     :  in std_logic;
          O_IPF      : out std_logic;
          O_IRDATA   : out std_logic_vector(15 downto 0 );
          O_IPIRDATA : out std_logic_vector(15 downto 0 )
          );
end component;

component SREG
    generic( SEGWIDTH : integer ); 
    port( I_CLK       :  in std_logic;
	      I_RST       :  in std_logic;
	      I_DATA      :  in std_logic_vector(SEGWIDTH-1 downto 0 ); --register in
		  I_RDSR      :  in std_logic; --Read signal                             
		  I_WRSR      :  in std_logic; --write signal
		  I_RDIP      :  in std_logic; --read IP signal (FETCH)     
     	  I_SRSEL     :  in std_logic_vector( 1 downto 0 );--Signal to select a segment
		  O_SREGDATA  : out std_logic_vector(SEGWIDTH-1 downto 0 ); --register out
		  O_CS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
          O_DS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
		  O_SS_V      : out std_logic_vector(SEGWIDTH-1 downto 0 );
		  O_ES_V      : out std_logic_vector(SEGWIDTH-1 downto 0 )
		  ); 
end component;

component CFE
    port( I_CLK    :  in std_logic;
		  I_RST    :  in std_logic;
	      I_ENDRC  :  in std_logic; --end read cycle  => '1'
	 	  I_ENDWC  :  in std_logic; --end write cycle => '1'
	      I_FE     :  in std_logic; --fetch signal             
		  I_WRQUE  :  in std_logic; --write QUE => '1'
          I_RD     :  in std_logic; --read signal from EU
          I_WR     :  in std_logic; --write signal from EU
		  I_RDSR   :  in std_logic; --SR read signal
          I_WRSR   :  in std_logic; --write SR signal
		  I_WRIP   :  in std_logic; --write IP signal
		  I_WRIR   :  in std_logic; --write IR signal
		  I_EUCRST :  in std_logic; --from EUC reset signal
		  I_NFE    :  in std_logic; --from EUC not fetch signal
		  I_HLT    :  in std_logic; --HLT signal
		  O_NOP_V  : out std_logic;    
 		  O_RDSR   : out std_logic; --register read signal
          O_RDIP   : out std_logic; --IP register read signal(fetch)
		  O_RDIR   : out std_logic  --IR register read signal
		  );
end component;

component CSEG
 	port( I_RM         :  in std_logic_vector( 2 downto 0); --r/m from CU
          I_MOD        :  in std_logic_vector( 1 downto 0); --MOD from CU
          I_CSR        :  in std_logic; --'1'=>SSEG from CU |'0'=>SSEG from CSEG 
		  I_SRSEL      :  in std_logic_vector( 1 downto 0); --when STRING,STACK, assignment SSEG
		  I_ORPCSR     :  in std_logic; --override prefix => '1'
		  I_ORPSRSEL   :  in std_logic_vector( 1 downto 0); --segment register when override prefix
          O_SRSEL : out std_logic_vector( 1 downto 0) --select segment signal
		  ); 
end component;

component MPX2IN1OUT
	generic( WID : integer := 16 
			 ); 
    port( I_SW     :  in std_logic;
          I_DATA0  :  in std_logic_vector( WID-1 downto 0);
          I_DATA1  :  in std_logic_vector( WID-1 downto 0);
          O_DATA   : out std_logic_vector( WID-1 downto 0)
		  );
end component;

component NEXTIP
    port( I_CLK     :  in std_logic;                            
          I_RST     :  in std_logic;
		  I_DATA    :  in std_logic_vector(15 downto 0 ); --input data 
		  I_WRIP    :  in std_logic; --WRITE IP signal
		  I_WRPLUS  :  in std_logic; --plus write signal
          I_PLUSOP  :  in std_logic_vector( 2 downto 0 ); --+1,+2,+3,+4,
		  I_PLUSMOD :  in std_logic_vector( 1 downto 0 ); --+1,+2,
          O_NEXTIP  : out std_logic_vector(15 downto 0 ) --OUT next IP data
		  ); 
end component; 

begin
 
	IPIR_TSREG : IPIR
	port map( 
		I_CLK => I_CLK,
        I_RST => I_RST,
        I_RDIP => CFE_RDIP,
        I_RDIR => CFE_RDIR,
        I_WRIP => I_WRIP,
        I_WRIR => I_WRIR,
        I_DATA => EUMMPX_DATA,
        I_EARQ => I_EARQ,
        O_IPF => O_IPF,
        O_IRDATA => O_IRDATA,
        O_IPIRDATA => O_IPIRDATA
        );
 
	SREG_TSREG : SREG
    generic map( 
		SEGWIDTH => 16
		)
    port map( 
		I_CLK => I_CLK,
	    I_RST => I_RST,
	    I_DATA => EUMMPX_DATA,
		I_RDSR => CFE_RDSR,
		I_WRSR => I_WRSR,
		I_RDIP => CFE_RDIP,
     	I_SRSEL => CSEG_SRSEL,
		O_SREGDATA => O_SREGDATA,
		O_CS_V => O_CS_V,
        O_DS_V => O_DS_V,
		O_SS_V => O_SS_V,
		O_ES_V => O_ES_V
		); 
 
	CFE_TSREG : CFE
    port map( 
		I_CLK => I_CLK,
		I_RST => I_RST,
	    I_ENDRC => I_ENDRC,
	 	I_ENDWC => I_ENDWC,
	    I_FE => I_FE,
		I_WRQUE => I_WRQUE,
        I_RD => I_RD,
        I_WR => I_WR,
		I_RDSR => I_RDSR,
        I_WRSR => I_WRSR,
		I_WRIP => I_WRIP,
		I_WRIR => I_WRIR,
		I_EUCRST => I_EUCRST,
		I_NFE => I_NFE,
		I_HLT => I_HLT,
		O_NOP_V => O_NOP_V,
 		O_RDSR => CFE_RDSR,
        O_RDIP => CFE_RDIP,
		O_RDIR => CFE_RDIR
		);
 
	CSEG_TSREG : CSEG
	port map( 
		I_RM => I_RM,
        I_MOD => I_MOD,
        I_CSR => I_CSR,
		I_SRSEL => I_SRSEL,
		I_ORPCSR => I_ORPCSR,
		I_ORPSRSEL => I_ORPSRSEL,
        O_SRSEL => CSEG_SRSEL
		); 
 
	MPX2IN1OUT_TSREG : MPX2IN1OUT
    port map( 
		I_SW => I_MDTF,
        I_DATA0 => I_EUDATA,
        I_DATA1 => I_BIUDATA,
        O_DATA => EUMMPX_DATA
		);
 
	NEXTIP_TSREG : NEXTIP
    port map( 
		I_CLK => I_CLK,                 
        I_RST => I_RST,
		I_DATA => EUMMPX_DATA,
		I_WRIP => I_WRIP,
		I_WRPLUS => I_WRPLUS,
        I_PLUSOP => I_PLUSOP,
		I_PLUSMOD => I_PLUSMOD,
        O_NEXTIP => O_NEXTIP
		); 

	O_IRF   <= CFE_RDIR;

end RTL;