mbcu.vhd

X8086的VHDL源码

-----------------------------------
--   FILE NAME : BCU_BCU.vhd
--   FUNCTION  : BUS Control Unit
--   AUTHOR    : Kazuma Mishima
--   DATE      : 5,6/2001
------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.UPAC.all;
entity MBCU is
    port ( I_CLK		:  in std_logic;
		   I_RST        :  in std_logic;
		   I_RDY        :  in std_logic; --if '0', BUS cycle become idle state.
		   I_EUCRST     :  in std_logic; --from EUC reset signal
	       I_DATA2MEM   :  in std_logic_vector(15 downto 0); --data in from DC
           I_PADR       :  in std_logic_vector(19 downto 0); --address in form DC
           I_RD         :  in std_logic; --signal read from memory
           I_WR         :  in std_logic; --signal write to memory 
           I_FE         :  in std_logic; --signal fetch from DC
		   I_EXTBUS     :  in std_logic_vector(15 downto 0); --external address/data 16bit bus
		   O_DATA2EU    : out std_logic_vector(15 downto 0); --data out to DC
           O_A19A16     : out std_logic_vector( 3 downto 0); --output adress 19~16bit
		   O_EXTBUS     : out std_logic_vector(15 downto 0); --external address/data 16bit bus
		   O_RD_N       : out std_logic; --when read from I/O device = 'L'
           O_WR_N       : out std_logic; --when write to I/O device = 'L'
           O_DEN_N      : out std_logic; --if there are effective data on the AD_BUS ='L'
		   O_ALE        : out std_logic; --if output adress = 'H'
           O_DTR        : out std_logic; --if data out to RAM = 'H' 
		   O_ENDBC      : out std_logic; --end 1 bus cycle = '1' 
		   O_BCUSTATE_V : out std_logic_vector( 2 downto 0) --current state(test)
           ); 
end MBCU;

architecture RTL of MBCU is

type   STATE is (T0,Tr1,Tr2,Tr3,Tw1,Tw2,Tw3);
signal current_state : STATE;
signal next_state    : STATE;
signal ebus          : std_logic_vector(15 downto 0); --stock DATA

begin

	O_DATA2EU <= I_EXTBUS; --data out ODC_DATA
	O_A19A16 <= I_PADR(19 downto 16);

--NEXT STATE 
	process(I_CLK,I_RST,I_EUCRST,next_state)
	begin 
		if (I_RST = RST_ACT) then
			current_state <= T0;
		elsif (I_CLK'event and I_CLK='0') then
			if (I_EUCRST = '1') then
				current_state <= T0;
			else
				current_state <= next_state;
			end if;
		end if;
	end process;
	
	process(current_state,I_DATA2MEM,I_PADR(15 downto 0))
	begin
		if (current_state = Tw2 or current_state = Tw3) then
			O_EXTBUS <= I_DATA2MEM;
		else
			O_EXTBUS <= I_PADR(15 downto 0);
		end if;
	end process;

--SEQUENCE PART
	process(current_state)
	begin
		case current_state is		  	
		when T0  => --initial state
			O_DTR    <= '0';
			O_ALE    <= '0';
			O_ENDBC  <= '0';
			O_RD_N   <= '1';
			O_WR_N   <= '1';
			O_DEN_N  <= '1';
		when Tr1 => --read bus cycle 1
			O_DTR    <= '0';
			O_ALE    <= '1';
			O_ENDBC  <= '0';
			O_RD_N   <= '1';
			O_WR_N   <= '1';
			O_DEN_N  <= '1';
		when Tr2 => --read bus cycle 2
			O_DTR    <= '0';
			O_ALE    <= '0';
			O_ENDBC  <= '0';
			O_RD_N   <= '0';
			O_WR_N   <= '1';
			O_DEN_N  <= '0';
		when Tr3 => --read bus cycle 3
			O_DTR    <= '0';
			O_ALE    <= '0';
			O_ENDBC  <= '1';
			O_RD_N   <= '0';
			O_WR_N   <= '1';
			O_DEN_N  <= '0';
		when Tw1 => --write bus cycle 1
			O_DTR    <= '1';
			O_ALE    <= '1';
			O_ENDBC  <= '0';
			O_RD_N   <= '1';
			O_WR_N   <= '1';
			O_DEN_N  <= '1';
		when Tw2 => --write bus cycle 2
			O_DTR    <= '1';
			O_ALE    <= '0';
			O_ENDBC  <= '0';
			O_RD_N   <= '1';
			O_WR_N   <= '0';
			O_DEN_N  <= '0';
		when Tw3 => --write bus cycle 3
			O_DTR    <= '1';
			O_ALE    <= '0';
			O_ENDBC  <= '1';
			O_RD_N   <= '1';
			O_WR_N   <= '0';
			O_DEN_N  <= '0';
		when others =>
			O_DTR    <= 'X';
			O_ALE    <= 'X';
			O_ENDBC  <= 'X';
			O_RD_N   <= 'X';
			O_WR_N   <= 'X';
			O_DEN_N  <= 'X';
		end case;
	end process;			
--FSM
	NEXT_STATE : 
	process (current_state,I_RD,I_WR,I_FE,I_RDY) 
	begin
		case current_state is  
		when T0 => --When active signal READ or WRITE or Fetch
			if   ((I_RD = '1' and I_WR = '0' and I_FE = '0') 
			or    (I_RD = '0' and I_WR = '0' and I_FE = '1'))then
				next_state <= Tr1;
			--When active signal WRITE
			elsif (I_RD = '0' and I_WR = '1' and I_FE = '0')then
				next_state <= Tw1;
			else 
				next_state <= T0;
			end if;
		when Tr1 => --READ or Fetch
			next_state <= Tr2;
		when Tr2 => 
			if (I_RDY = '1')then
				next_state <= Tr3; 
			else --idle         
				next_state <= Tr2;
			end if;
		when Tr3 => 
			next_state <= T0;
		when Tw1 => --WRITE
			next_state <= Tw2;
		when Tw2 => 
			if (I_RDY = '1')then
				next_state <= Tw3; 
			else  --idle         
				next_state <= Tw2;
			end if;
		when Tw3 => 
			next_state <= T0;
		when others => 
			next_state <= T0;
		end case;
	end process;

	BCUSTATE_V : 
	process(current_state)
	begin
		case current_state is
		when T0     => O_BCUSTATE_V <= "000";
		when Tr1    => O_BCUSTATE_V <= "001";
		when Tr2    => O_BCUSTATE_V <= "010";
		when Tr3    => O_BCUSTATE_V <= "011";
		when Tw1    => O_BCUSTATE_V <= "100";
		when Tw2    => O_BCUSTATE_V <= "101";
		when Tw3    => O_BCUSTATE_V <= "110";
		when others => O_BCUSTATE_V <= "111";
		end case; 
	end process;

end RTL;