mp8086.eda.talkback.xml

X8086的VHDL源码

<!--
This XML file (created on Tue Jan 09 23:45:12 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>0090cccb6bda</host_id>
	<nic_id>000e0c2c3096</nic_id>
	<cdrive_id>b4be55b0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_eda</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Tue Jan 09 23:45:12 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2600</cpu_freq>
	</cpu>
	<ram units="MB">1015</ram>
</machine>
<project>C:/work/MP8086/MP8086</project>
<revision>MP8086</revision>
<compilation_summary>
	<flow_status>Successful - Tue Jan 09 23:45:12 2007</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>MP8086</revision_name>
	<top_level_entity_name>MP8086</top_level_entity_name>
	<family>Stratix</family>
	<met_timing_requirements>Yes</met_timing_requirements>
	<total_logic_elements>5,126 / 18,460 ( 28 % )</total_logic_elements>
	<total_pins>426 / 587 ( 73 % )</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>4,096 / 1,669,248 ( &lt; 1 % )</total_memory_bits>
	<dsp_block_9_bit_elements>0 / 80 ( 0 % )</dsp_block_9_bit_elements>
	<total_plls>0 / 6 ( 0 % )</total_plls>
	<total_dlls>0 / 2 ( 0 % )</total_dlls>
	<device>EP1S20F780C5</device>
	<timing_models>Final</timing_models>
</compilation_summary>
<mep_data>
	<command_line>quartus_eda --read_settings_files=on --write_settings_files=off MP8086 -c MP8086 --gen_testbench</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<info>Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings</info>
	<info>Info: Elapsed time: 00:00:28</info>
	<info>Info: Processing ended: Tue Jan 09 23:45:12 2007</info>
	<info>Info: Generated VHDL Test Bench File C:/work/MP8086/simulation/modelsim/MP8086.vht for simulation</info>
	<info>Info: Command: quartus_eda --read_settings_files=on --write_settings_files=off MP8086 -c MP8086 --gen_testbench</info>
</messages>
</talkback>