mp8086.map.talkback.xml

X8086的VHDL源码

<!--
This XML file (created on Fri Jan 12 16:24:50 2007) contains limited information
from the compilation of logic designs using Quartus II software (BUT NOT THE
LOGIC DESIGN FILES) that will be transmitted to Altera Corporation through
operation of the "TalkBack" feature.  To enable/disable this feature, run
qtb_install.exe located in your quartus/bin folder.  For more information, go
to license.txt.
-->
<talkback>
<ver>6.0</ver>
<schema>quartus_version_6.0_build_178.xsd</schema>
<license>
	<host_id>0090cccb6bda</host_id>
	<nic_id>000e0c2c3096</nic_id>
	<cdrive_id>b4be55b0</cdrive_id>
</license>
<tool>
	<name>Quartus II</name>
	<version>6.0</version>
	<build>Build 178</build>
	<binary_type>32</binary_type>
	<module>quartus_map</module>
	<edition>Full Version</edition>
	<eval>Licensed</eval>
	<compilation_end_time>Fri Jan 12 16:24:51 2007</compilation_end_time>
</tool>
<machine>
	<os>Windows XP</os>
	<cpu>
		<proc_count>2</proc_count>
		<cpu_freq units="MHz">2600</cpu_freq>
	</cpu>
	<ram units="MB">1015</ram>
</machine>
<project>C:/work/MP8086/MP8086</project>
<revision>MP8086</revision>
<compilation_summary>
	<flow_status>Successful - Fri Jan 12 16:24:50 2007</flow_status>
	<quartus_ii_version>6.0 Build 178 04/27/2006 SJ Full Version</quartus_ii_version>
	<revision_name>MP8086</revision_name>
	<top_level_entity_name>MP8086</top_level_entity_name>
	<family>APEX20KE</family>
	<device>EP20K400EBC652-3</device>
	<timing_models>Final</timing_models>
	<met_timing_requirements>N/A</met_timing_requirements>
	<total_logic_elements>5,721</total_logic_elements>
	<total_pins>426</total_pins>
	<total_virtual_pins>0</total_virtual_pins>
	<total_memory_bits>4,096</total_memory_bits>
	<total_plls>0</total_plls>
</compilation_summary>
<mep_data>
	<command_line>quartus_map --read_settings_files=on --write_settings_files=off MP8086 -c MP8086</command_line>
</mep_data>
<software_data>
	<smart_recompile>off</smart_recompile>
</software_data>
<messages>
	<warning>Warning: Output pins are stuck at VCC or GND</warning>
	<warning>Warning: Pin &quot;O_7SEGDATA8[0]&quot; stuck at GND</warning>
	<warning>Warning: Pin &quot;O_7SEGDATA7[0]&quot; stuck at GND</warning>
	<warning>Warning: Pin &quot;O_7SEGDATA6[0]&quot; stuck at GND</warning>
	<warning>Warning: Pin &quot;O_7SEGDATA5[0]&quot; stuck at GND</warning>
	<info>Info: Quartus II Analysis &amp; Synthesis was successful. 0 errors, 9 warnings</info>
	<info>Info: Elapsed time: 00:01:04</info>
	<info>Info: Processing ended: Fri Jan 12 16:24:50 2007</info>
	<info>Info: Implemented 6163 device resources after synthesis - the final resource count might be different</info>
	<info>Info: Implemented 16 RAM segments</info>
</messages>
<analysis___synthesis_settings>
	<row>
		<option>Device</option>
		<setting>EP20K400EBC652-3</setting>
	</row>
	<row>
		<option>Top-level entity name</option>
		<setting>MP8086</setting>
		<default_value>MP8086</default_value>
	</row>
	<row>
		<option>Family name</option>
		<setting>APEX20KE</setting>
		<default_value>Stratix</default_value>
	</row>
	<row>
		<option>Use smart compilation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Create Debugging Nodes for IP Cores</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Preserve fewer node names</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Disable OpenCore Plus hardware evaluation</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Verilog Version</option>
		<setting>Verilog_2001</setting>
		<default_value>Verilog_2001</default_value>
	</row>
	<row>
		<option>VHDL Version</option>
		<setting>VHDL93</setting>
		<default_value>VHDL93</default_value>
	</row>
	<row>
		<option>State Machine Processing</option>
		<setting>Auto</setting>
		<default_value>Auto</default_value>
	</row>
	<row>
		<option>Extract Verilog State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Extract VHDL State Machines</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Add Pass-Through Logic to Inferred RAMs</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>NOT Gate Push-Back</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Power-Up Don&apos;t Care</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Redundant Logic Cells</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Remove Duplicate Registers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore CARRY Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore CASCADE Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore ROW GLOBAL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore LCELL Buffers</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore SOFT Buffers</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Limit AHDL Integers to 32 Bits</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Auto Implement in ROM</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Technology Mapper -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur</option>
		<setting>LUT</setting>
		<default_value>LUT</default_value>
	</row>
	<row>
		<option>Optimization Technique -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur</option>
		<setting>Balanced</setting>
		<default_value>Balanced</default_value>
	</row>
	<row>
		<option>Allow XOR Gate Usage</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Carry Chain Length</option>
		<setting>48</setting>
		<default_value>48</default_value>
	</row>
	<row>
		<option>Cascade Chain Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>Parallel Expander Chain Length -- APEX 20K/APEX 20KE/APEX 20KC/APEX II/ARM-based Excalibur</option>
		<setting>16</setting>
		<default_value>16</default_value>
	</row>
	<row>
		<option>Auto Carry Chains</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Parallel Expanders</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Open-Drain Pins</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Remove Duplicate Logic</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Perform WYSIWYG Primitive Resynthesis</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Perform gate-level register retiming</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow register retiming to trade off Tsu/Tco with Fmax</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto ROM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto RAM Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Shift Register Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Clock Enable Replacement</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Auto Resource Sharing</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any RAM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any ROM Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Allow Any Shift Register Size For Recognition</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Ignore translate_off and translate_on Synthesis Directives</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Show Parameter Settings Tables in Synthesis Report</option>
		<setting>On</setting>
		<default_value>On</default_value>
	</row>
	<row>
		<option>Ignore Maximum Fan-Out Assignments</option>
		<setting>Off</setting>
		<default_value>Off</default_value>
	</row>
	<row>
		<option>Retiming Meta-Stability Register Sequence Length</option>
		<setting>2</setting>
		<default_value>2</default_value>
	</row>
	<row>
		<option>HDL message level</option>
		<setting>Level2</setting>
		<default_value>Level2</default_value>
	</row>
</analysis___synthesis_settings>
<general_register_statistics>
	<row>
		<statistic>Total registers</statistic>
		<value>1040</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Clear</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Synchronous Load</statistic>
		<value>23</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Clear</statistic>
		<value>548</value>
	</row>
	<row>
		<statistic>Number of registers using Asynchronous Load</statistic>
		<value>0</value>
	</row>
	<row>
		<statistic>Number of registers using Clock Enable</statistic>
		<value>532</value>
	</row>
	<row>
		<statistic>Number of registers using Preset</statistic>
		<value>0</value>
	</row>
</general_register_statistics>
</talkback>