pcpu.fit.eqn

来自「可以实现CPU的VHDL源码」· EQN 代码 · 共 2,434 行 · 第 1/5 页

reg_C[8]_lut_out = F3_cs_buffer[8];
reg_C[8] = DFFE(reg_C[8]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L675 is i~5974 at LC10_1_AI4
--operation mode is normal

A1L675 = select_y[0] & !select_y[2] & reg_C[8] # !select_y[0] & select_y[2] & id_ir[8];


--A1L773 is i~500 at LC3_7_AI4
--operation mode is normal

A1L773 = A1L673 & (A1L675 # !select_y[3]) # !A1L673 & select_y[3] & A1L383;


--reg_B[7] is reg_B[7] at LC5_4_AJ4
--operation mode is normal

reg_B[7]_lut_out = A1L472 # A1L372 # A1L515 & A1L652;
reg_B[7] = DFFE(reg_B[7]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_C1[7] is reg_C1[7] at LC5_9_AJ4
--operation mode is normal

reg_C1[7]_lut_out = A1L785 & reg_C[7] # !A1L785 & (mem_ir[11] & reg_C[7] # !mem_ir[11] & d_datain[7]);
reg_C1[7] = DFFE(reg_C1[7]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_A[7] is reg_A[7] at LC10_9_AJ4
--operation mode is normal

reg_A[7]_lut_out = !A1L522;
reg_A[7] = DFFE(reg_A[7]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L093 is i~513 at LC3_14_AJ4
--operation mode is normal

A1L093 = select_y[2] & (select_y[0] # reg_C1[7]) # !select_y[2] & reg_A[7] & !select_y[0];


--smdr[7] is smdr[7] at LC2_10_AJ4
--operation mode is normal

smdr[7]_lut_out = A1L564 & (A1L906 # id_ir[10]) # !A1L564 & A1L906 & !id_ir[10];
smdr[7] = DFFE(smdr[7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L447);


--A1L193 is i~514 at LC1_14_AJ4
--operation mode is normal

A1L193 = A1L093 & (smdr[7] # !select_y[0]) # !A1L093 & reg_B[7] & select_y[0];


--gr[6][7] is gr[6][7] at LC6_9_AJ4
--operation mode is normal

gr[6][7]_lut_out = reg_C1[7];
gr[6][7] = DFFE(gr[6][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L461);


--gr[3][7] is gr[3][7] at LC9_12_AJ4
--operation mode is normal

gr[3][7]_lut_out = reg_C1[7];
gr[3][7] = DFFE(gr[3][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L011);


--gr[2][7] is gr[2][7] at LC6_13_AJ4
--operation mode is normal

gr[2][7]_lut_out = reg_C1[7];
gr[2][7] = DFFE(gr[2][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L29);


--A1L883 is i~511 at LC10_14_AJ4
--operation mode is normal

A1L883 = select_y[0] & (gr[3][7] # select_y[2]) # !select_y[0] & !select_y[2] & gr[2][7];


--gr[7][7] is gr[7][7] at LC3_15_AJ4
--operation mode is normal

gr[7][7]_lut_out = reg_C1[7];
gr[7][7] = DFFE(gr[7][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L281);


--A1L983 is i~512 at LC5_14_AJ4
--operation mode is normal

A1L983 = A1L883 & (gr[7][7] # !select_y[2]) # !A1L883 & select_y[2] & gr[6][7];


--gr[1][7] is gr[1][7] at LC6_12_AJ4
--operation mode is normal

gr[1][7]_lut_out = reg_C1[7];
gr[1][7] = DFFE(gr[1][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L47);


--gr[4][7] is gr[4][7] at LC10_13_AJ4
--operation mode is normal

gr[4][7]_lut_out = reg_C1[7];
gr[4][7] = DFFE(gr[4][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L821);


--A1L683 is i~509 at LC3_12_AJ4
--operation mode is normal

A1L683 = select_y[2] & (select_y[0] # gr[4][7]) # !select_y[2] & !select_y[0] & G1_q[7];


--gr[5][7] is gr[5][7] at LC8_11_AJ4
--operation mode is normal

gr[5][7]_lut_out = reg_C1[7];
gr[5][7] = DFFE(gr[5][7]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L641);


--A1L783 is i~510 at LC5_12_AJ4
--operation mode is normal

A1L783 = A1L683 & (gr[5][7] # !select_y[0]) # !A1L683 & gr[1][7] & select_y[0];


--A1L483 is i~507 at LC2_13_AJ4
--operation mode is normal

A1L483 = select_y[1] & (select_y[3] # A1L983) # !select_y[1] & !select_y[3] & A1L783;


--id_ir[7] is id_ir[7] at LC5_3_AJ4
--operation mode is normal

id_ir[7]_lut_out = i_datain[7];
id_ir[7] = DFFE(id_ir[7]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L775 is i~5975 at LC9_3_AJ4
--operation mode is normal

A1L775 = select_y[0] & reg_C[7] & !select_y[2] # !select_y[0] & select_y[2] & id_ir[7];


--A1L583 is i~508 at LC1_13_AJ4
--operation mode is normal

A1L583 = A1L483 & (A1L775 # !select_y[3]) # !A1L483 & A1L193 & select_y[3];


--reg_C1[6] is reg_C1[6] at LC3_15_Z4
--operation mode is normal

reg_C1[6]_lut_out = mem_ir[11] & reg_C[6] # !mem_ir[11] & (A1L785 & reg_C[6] # !A1L785 & d_datain[6]);
reg_C1[6] = DFFE(reg_C1[6]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_B[6] is reg_B[6] at LC7_10_AK4
--operation mode is normal

reg_B[6]_lut_out = A1L772 # A1L672 # A1L915 & A1L652;
reg_B[6] = DFFE(reg_B[6]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_A[6] is reg_A[6] at LC6_2_AL4
--operation mode is normal

reg_A[6]_lut_out = !A1L922;
reg_A[6] = DFFE(reg_A[6]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L893 is i~521 at LC5_11_AK4
--operation mode is normal

A1L893 = select_y[0] & (select_y[2] # reg_B[6]) # !select_y[0] & reg_A[6] & !select_y[2];


--smdr[6] is smdr[6] at LC1_2_AL4
--operation mode is normal

smdr[6]_lut_out = A1L764 & (id_ir[10] # A1L116) # !A1L764 & !id_ir[10] & A1L116;
smdr[6] = DFFE(smdr[6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L447);


--A1L993 is i~522 at LC9_15_AL4
--operation mode is normal

A1L993 = A1L893 & (smdr[6] # !select_y[2]) # !A1L893 & reg_C1[6] & select_y[2];


--gr[3][6] is gr[3][6] at LC9_7_AL4
--operation mode is normal

gr[3][6]_lut_out = reg_C1[6];
gr[3][6] = DFFE(gr[3][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L011);


--gr[6][6] is gr[6][6] at LC9_8_AJ4
--operation mode is normal

gr[6][6]_lut_out = reg_C1[6];
gr[6][6] = DFFE(gr[6][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L461);


--gr[2][6] is gr[2][6] at LC8_12_AI4
--operation mode is normal

gr[2][6]_lut_out = reg_C1[6];
gr[2][6] = DFFE(gr[2][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L29);


--A1L693 is i~519 at LC3_10_AK4
--operation mode is normal

A1L693 = select_y[2] & (gr[6][6] # select_y[0]) # !select_y[2] & gr[2][6] & !select_y[0];


--gr[7][6] is gr[7][6] at LC7_16_AH4
--operation mode is normal

gr[7][6]_lut_out = reg_C1[6];
gr[7][6] = DFFE(gr[7][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L281);


--A1L793 is i~520 at LC5_10_AK4
--operation mode is normal

A1L793 = A1L693 & (gr[7][6] # !select_y[0]) # !A1L693 & select_y[0] & gr[3][6];


--gr[4][6] is gr[4][6] at LC7_2_AJ4
--operation mode is normal

gr[4][6]_lut_out = reg_C1[6];
gr[4][6] = DFFE(gr[4][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L821);


--gr[1][6] is gr[1][6] at LC2_15_AL4
--operation mode is normal

gr[1][6]_lut_out = reg_C1[6];
gr[1][6] = DFFE(gr[1][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L47);


--A1L493 is i~517 at LC3_14_AL4
--operation mode is normal

A1L493 = select_y[0] & (select_y[2] # gr[1][6]) # !select_y[0] & !select_y[2] & G1_q[6];


--gr[5][6] is gr[5][6] at LC3_16_AH4
--operation mode is normal

gr[5][6]_lut_out = reg_C1[6];
gr[5][6] = DFFE(gr[5][6]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L641);


--A1L593 is i~518 at LC2_14_AL4
--operation mode is normal

A1L593 = A1L493 & (gr[5][6] # !select_y[2]) # !A1L493 & gr[4][6] & select_y[2];


--A1L293 is i~515 at LC10_15_AL4
--operation mode is normal

A1L293 = select_y[1] & (select_y[3] # A1L793) # !select_y[1] & !select_y[3] & A1L593;


--id_ir[6] is id_ir[6] at LC3_6_X4
--operation mode is normal

id_ir[6]_lut_out = i_datain[6];
id_ir[6] = DFFE(id_ir[6]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L875 is i~5976 at LC1_15_AL4
--operation mode is normal

A1L875 = select_y[0] & reg_C[6] & !select_y[2] # !select_y[0] & id_ir[6] & select_y[2];


--A1L393 is i~516 at LC8_15_AL4
--operation mode is normal

A1L393 = A1L293 & (A1L875 # !select_y[3]) # !A1L293 & select_y[3] & A1L993;


--reg_B[5] is reg_B[5] at LC7_3_AJ4
--operation mode is normal

reg_B[5]_lut_out = A1L082 # A1L972 # A1L652 & A1L325;
reg_B[5] = DFFE(reg_B[5]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_C1[5] is reg_C1[5] at LC9_9_AJ4
--operation mode is normal

reg_C1[5]_lut_out = A1L785 & reg_C[5] # !A1L785 & (mem_ir[11] & reg_C[5] # !mem_ir[11] & d_datain[5]);
reg_C1[5] = DFFE(reg_C1[5]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_A[5] is reg_A[5] at LC6_1_AJ4
--operation mode is normal

reg_A[5]_lut_out = !A1L332;
reg_A[5] = DFFE(reg_A[5]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L604 is i~529 at LC3_2_AJ4
--operation mode is normal

A1L604 = select_y[2] & (select_y[0] # reg_C1[5]) # !select_y[2] & !select_y[0] & reg_A[5];


--smdr[5] is smdr[5] at LC3_1_AJ4
--operation mode is normal

smdr[5]_lut_out = id_ir[10] & A1L964 # !id_ir[10] & A1L316;
smdr[5] = DFFE(smdr[5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L447);


--A1L704 is i~530 at LC1_2_AJ4
--operation mode is normal

A1L704 = A1L604 & (smdr[5] # !select_y[0]) # !A1L604 & select_y[0] & reg_B[5];


--gr[6][5] is gr[6][5] at LC4_9_AJ4
--operation mode is normal

gr[6][5]_lut_out = reg_C1[5];
gr[6][5] = DFFE(gr[6][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L461);


--gr[3][5] is gr[3][5] at LC7_12_AJ4
--operation mode is normal

gr[3][5]_lut_out = reg_C1[5];
gr[3][5] = DFFE(gr[3][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L011);


--gr[2][5] is gr[2][5] at LC7_13_AJ4
--operation mode is normal

gr[2][5]_lut_out = reg_C1[5];
gr[2][5] = DFFE(gr[2][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L29);


--A1L404 is i~527 at LC4_3_AJ4
--operation mode is normal

A1L404 = select_y[0] & (select_y[2] # gr[3][5]) # !select_y[0] & !select_y[2] & gr[2][5];


--gr[7][5] is gr[7][5] at LC6_13_AH4
--operation mode is normal

gr[7][5]_lut_out = reg_C1[5];
gr[7][5] = DFFE(gr[7][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L281);


--A1L504 is i~528 at LC10_2_AJ4
--operation mode is normal

A1L504 = A1L404 & (gr[7][5] # !select_y[2]) # !A1L404 & select_y[2] & gr[6][5];


--gr[1][5] is gr[1][5] at LC7_10_AJ4
--operation mode is normal

gr[1][5]_lut_out = reg_C1[5];
gr[1][5] = DFFE(gr[1][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L47);


--gr[4][5] is gr[4][5] at LC8_14_AJ4
--operation mode is normal

gr[4][5]_lut_out = reg_C1[5];
gr[4][5] = DFFE(gr[4][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L821);


--A1L204 is i~525 at LC7_15_AJ4
--operation mode is normal

A1L204 = select_y[2] & (select_y[0] # gr[4][5]) # !select_y[2] & !select_y[0] & G1_q[5];


--gr[5][5] is gr[5][5] at LC7_11_AJ4
--operation mode is normal

gr[5][5]_lut_out = reg_C1[5];
gr[5][5] = DFFE(gr[5][5]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L641);


--A1L304 is i~526 at LC6_3_AJ4
--operation mode is normal

A1L304 = A1L204 & (gr[5][5] # !select_y[0]) # !A1L204 & select_y[0] & gr[1][5];


--A1L004 is i~523 at LC2_2_AJ4
--operation mode is normal

A1L004 = select_y[1] & (select_y[3] # A1L504) # !select_y[1] & !select_y[3] & A1L304;


--id_ir[5] is id_ir[5] at LC8_6_AI4
--operation mode is normal

id_ir[5]_lut_out = i_datain[5];
id_ir[5] = DFFE(id_ir[5]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L975 is i~5977 at LC8_3_AJ4
--operation mode is normal

A1L975 = select_y[2] & id_ir[5] & !select_y[0] # !select_y[2] & select_y[0] & reg_C[5];


--A1L104 is i~524 at LC4_2_AJ4
--operation mode is normal

A1L104 = A1L004 & (A1L975 # !select_y[3]) # !A1L004 & A1L704 & select_y[3];


--reg_C1[4] is reg_C1[4] at LC7_6_AJ4
--operation mode is normal

reg_C1[4]_lut_out = A1L785 & reg_C[4] # !A1L785 & (mem_ir[11] & reg_C[4] # !mem_ir[11] & d_datain[4]);
reg_C1[4] = DFFE(reg_C1[4]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_B[4] is reg_B[4] at LC6_3_AK4
--operation mode is normal

reg_B[4]_lut_out = A1L382 # A1L282 # A1L652 & A1L725;
reg_B[4] = DFFE(reg_B[4]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--reg_A[4] is reg_A[4] at LC10_2_AK4
--operation mode is normal

reg_A[4]_lut_out = !A1L732;
reg_A[4] = DFFE(reg_A[4]_lut_out, GLOBAL(clock), GLOBAL(reset), , state);


--A1L414 is i~537 at LC4_12_AK4
--operation mode is normal

A1L414 = select_y[0] & (reg_B[4] # select_y[2]) # !select_y[0] & !select_y[2] & reg_A[4];


--smdr[4] is smdr[4] at LC5_5_AJ4
--operation mode is normal

smdr[4]_lut_out = id_ir[10] & A1L174 # !id_ir[10] & A1L516;
smdr[4] = DFFE(smdr[4]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L447);


--A1L514 is i~538 at LC5_6_AJ4
--operation mode is normal

A1L514 = A1L414 & (smdr[4] # !select_y[2]) # !A1L414 & reg_C1[4] & select_y[2];


--gr[3][4] is gr[3][4] at LC1_6_AJ4
--operation mode is normal

gr[3][4]_lut_out = reg_C1[4];
gr[3][4] = DFFE(gr[3][4]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L011);


--gr[6][4] is gr[6][4] at LC6_8_AJ4
--operation mode is normal

gr[6][4]_lut_out = reg_C1[4];
gr[6][4] = DFFE(gr[6][4]_lut_out, GLOBAL(clock), GLOBAL(reset), , A1L461);


--gr[2][4] is gr[2][4] at LC4_13_AJ4
--operation mode is normal