ap600.v

可以实现CPU的VHDL源码

// Project #2: 16-bit pipeline processor
// Design file

`include "pcpu.v" // Cpu module
`include "imem.v" // Instruction memory module
`include "dmem.v" // Data memory module

module AP600 (clk, reset, pswA, pswB, pswC, pswD, dipA, dipB, hexA, hexB,
	      buzzer, ledA, ledB, ledC, ledD, 
              segA, segB, segC, segD, segE, segF, segG, segH);

  input clk ,reset;                  // clock, reset
  input[4:0] pswA, pswB, pswC, pswD; // push switch(NEG)
  input[7:0] dipA, dipB;             // dip switch(NEG)
  input[3:0] hexA, hexB;             // rotary switch
  output     buzzer;		     // buzzer
  output[7:0] ledA, ledB, ledC, ledD;// LED
  output[7:0] segA, segB, segC, segD, segE, segF, segG, segH; // 7SEG

  wire [15:0] i_datain;
  wire [7:0] i_addr;
  wire [7:0] d_addr;
  wire [15:0] d_datain;
  wire [15:0] d_dataout;
  wire d_we;
  wire enable, start;

  // for test
  wire [3:0] select_y;
  wire [15:0] y;

  // for output
  wire [7:0]leda;
  wire [7:0]ledb;
  wire [7:0]ledc;
  wire [7:0]ledd;
  wire [7:0]lede;
  wire [7:0]ledf;
  wire [7:0]ledg;
  wire [7:0]ledh;

  // Input assignment
  assign select_y = hexA;
  assign enable = hexB[0];
  assign start = ~pswA[0];

  // Output assinment
  assign buzzer = 1'b0;
  assign ledA = {i_datain[8],i_datain[9],i_datain[10],i_datain[11],
                 i_datain[12],i_datain[13],i_datain[14],i_datain[15]};
  assign ledB = {i_datain[0],i_datain[1],i_datain[2],i_datain[3],
                 i_datain[4],i_datain[5],i_datain[6],i_datain[7]};
  assign ledC = {d_datain[8],d_datain[9],d_datain[10],d_datain[11],
                 d_datain[12],d_datain[13],d_datain[14],d_datain[15]};
  assign ledD = {d_datain[8],d_datain[9],d_datain[10],d_datain[11],
                 d_datain[12],d_datain[13],d_datain[14],d_datain[15]};
  assign segA = leda;
  assign segB = ledb;
  assign segC = ledc;
  assign segD = ledd;
  assign segE = lede;
  assign segF = ledf;
  assign segG = ledg;
  assign segH = ledh;

  // pipeline CPU top module
  pcpu pcpu (reset, clk, enable, start, i_addr, i_datain, d_addr,
             d_datain, d_dataout, d_we, select_y, y);

  // instruction memory
  imem imem (i_addr, ~pswB[0], ~clk, {dipA, dipB}, i_datain);
  // data memory
  dmem dmem (d_addr, d_we, ~clk, d_dataout, d_datain);

  // 7SEG output
  bin2led bleda (dipA[7:4], leda);
  bin2led bledb (dipA[3:0], ledb);
  bin2led bledc (dipB[7:4], ledc);
  bin2led bledd (dipB[3:0], ledd);

  bin2led blede (y[15:12], lede);
  bin2led bledf (y[11:8], ledf);
  bin2led bledg (y[7:4], ledg);
  bin2led bledh (y[3:0], ledh);

endmodule

// binary -> 7 SEG LED
module bin2led(in, out);
  input [3:0] in;
  output [7:0] out;
  reg [7:0] out;
 
  always @(in)
   begin
     case(in)
        0: out = 8'b11111100;
        1: out = 8'b01100000;
        2: out = 8'b11011010;
        3: out = 8'b11110010;
        4: out = 8'b01100110;
        5: out = 8'b10110110;
        6: out = 8'b10111110;
        7: out = 8'b11100000;
        8: out = 8'b11111110;
        9: out = 8'b11110110;
        10: out = 8'b11101110;
        11: out = 8'b00111110;
        12: out = 8'b00011010;
        13: out = 8'b01111010;
        14: out = 8'b10011110;
        15: out = 8'b10001110;
       default: out = 8'bxxxxxxxx;
      endcase
   end
endmodule