prev_cmp_pcpu.fit.qmsg

可以实现CPU的VHDL源码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 15 16:06:53 2008 " "Info: Processing started: Tue Jan 15 16:06:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off pcpu -c pcpu " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pcpu -c pcpu" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "pcpu EP20K30ETC144-1 " "Info: Automatically selected device EP20K30ETC144-1 for design pcpu" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0 "" 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "clock automatically " "Info: Promoted cell \"clock\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0 "" 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "reset automatically " "Info: Promoted cell \"reset\" to global signal automatically" {  } {  } 0 0 "Promoted cell \"%1!s!\" to global signal %2!s!" 0 0 "" 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Tue Jan 15 2008 16:07:45 " "Info: Started fitting attempt 1 on Tue Jan 15 2008 at 16:07:45" {  } {  } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:02 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "9 " "Info: Overall column FastTrack interconnect = 9%" {  } {  } 0 0 "Overall column FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "22 " "Info: Overall row FastTrack interconnect = 22%" {  } {  } 0 0 "Overall row FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "11 " "Info: Maximum column FastTrack interconnect = 11%" {  } {  } 0 0 "Maximum column FastTrack interconnect = %1!d!%%" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "34 " "Info: Maximum row FastTrack interconnect = 34%" {  } {  } 0 0 "Maximum row FastTrack interconnect = %1!d!%%" 0 0 "" 0}  } {  } 0 0 "Design requires the following device routing resources:" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.070 ns register register " "Info: Estimated most critical path is register to register delay of 9.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns gr\[6\]\[5\] 1 REG LAB_10_C1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_10_C1; Fanout = 4; REG Node = 'gr\[6\]\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { gr[6][5] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 207 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.934 ns) + CELL(0.890 ns) 2.985 ns Mux42~37 2 COMB LAB_9_C2 1 " "Info: 2: + IC(1.934 ns) + CELL(0.890 ns) = 2.985 ns; Loc. = LAB_9_C2; Fanout = 1; COMB Node = 'Mux42~37'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.824 ns" { gr[6][5] Mux42~37 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.890 ns) 4.121 ns Mux42~38 3 COMB LAB_9_C2 1 " "Info: 3: + IC(0.246 ns) + CELL(0.890 ns) = 4.121 ns; Loc. = LAB_9_C2; Fanout = 1; COMB Node = 'Mux42~38'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.136 ns" { Mux42~37 Mux42~38 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.222 ns) + CELL(0.890 ns) 6.233 ns reg_B~4987 4 COMB LAB_10_B2 1 " "Info: 4: + IC(1.222 ns) + CELL(0.890 ns) = 6.233 ns; Loc. = LAB_10_B2; Fanout = 1; COMB Node = 'reg_B~4987'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.112 ns" { Mux42~38 reg_B~4987 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.214 ns) + CELL(0.623 ns) 9.070 ns reg_B\[5\] 5 REG LAB_9_A1 2 " "Info: 5: + IC(2.214 ns) + CELL(0.623 ns) = 9.070 ns; Loc. = LAB_9_A1; Fanout = 2; REG Node = 'reg_B\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.837 ns" { reg_B~4987 reg_B[5] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 38.08 % ) " "Info: Total cell delay = 3.454 ns ( 38.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.616 ns ( 61.92 % ) " "Info: Total interconnect delay = 5.616 ns ( 61.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.070 ns" { gr[6][5] Mux42~37 Mux42~38 reg_B~4987 reg_B[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Info: Fitter placement operations ending: elapsed time is 00:00:07" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "202 " "Info: Allocated 202 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 15 16:07:55 2008 " "Info: Processing ended: Tue Jan 15 16:07:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:01:02 " "Info: Elapsed time: 00:01:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}