pcpu.tan.qmsg

可以实现CPU的VHDL源码

{ "Info" "ITDB_FULL_TPD_RESULT" "select_y\[3\] y\[6\] 5.191 ns Shortest " "Info: Shortest tpd from source pin \"select_y\[3\]\" to destination pin \"y\[6\]\" is 5.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns select_y\[3\] 1 PIN PIN_23 42 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_23; Fanout = 42; PIN Node = 'select_y\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { select_y[3] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.358 ns) 1.782 ns Mux57~109 2 COMB LC8_3_B2 1 " "Info: 2: + IC(0.534 ns) + CELL(0.358 ns) = 1.782 ns; Loc. = LC8_3_B2; Fanout = 1; COMB Node = 'Mux57~109'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.892 ns" { select_y[3] Mux57~109 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(2.410 ns) 5.191 ns y\[6\] 3 PIN PIN_10 0 " "Info: 3: + IC(0.999 ns) + CELL(2.410 ns) = 5.191 ns; Loc. = PIN_10; Fanout = 0; PIN Node = 'y\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.409 ns" { Mux57~109 y[6] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.658 ns ( 70.47 % ) " "Info: Total cell delay = 3.658 ns ( 70.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.533 ns ( 29.53 % ) " "Info: Total interconnect delay = 1.533 ns ( 29.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.191 ns" { select_y[3] Mux57~109 y[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.191 ns" { select_y[3] {} select_y[3]~out0 {} Mux57~109 {} y[6] {} } { 0.000ns 0.000ns 0.534ns 0.999ns } { 0.000ns 0.890ns 0.358ns 2.410ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Allocated 140 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 15 16:09:29 2008 " "Info: Processing ended: Tue Jan 15 16:09:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:44 " "Info: Elapsed time: 00:00:44" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}