pcpu.tan.qmsg

可以实现CPU的VHDL源码

{ "Info" "ITDB_FULL_TCO_RESULT" "clock y\[0\] pc\[0\] 16.123 ns register " "Info: tco from clock \"clock\" to destination pin \"y\[0\]\" through register \"pc\[0\]\" is 16.123 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.663 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns pc\[0\] 2 REG LC2_8_E1 4 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC2_8_E1; Fanout = 4; REG Node = 'pc\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.773 ns" { clock pc[0] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock pc[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} pc[0] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.125 ns + Longest register pin " "Info: + Longest register to pin delay is 14.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns pc\[0\] 1 REG LC2_8_E1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC2_8_E1; Fanout = 4; REG Node = 'pc\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { pc[0] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.650 ns) + CELL(0.890 ns) 3.701 ns Mux63~105 2 COMB LC1_8_C2 1 " "Info: 2: + IC(2.650 ns) + CELL(0.890 ns) = 3.701 ns; Loc. = LC1_8_C2; Fanout = 1; COMB Node = 'Mux63~105'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.540 ns" { pc[0] Mux63~105 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.358 ns) 4.312 ns Mux63~106 3 COMB LC3_8_C2 1 " "Info: 3: + IC(0.253 ns) + CELL(0.358 ns) = 4.312 ns; Loc. = LC3_8_C2; Fanout = 1; COMB Node = 'Mux63~106'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.611 ns" { Mux63~105 Mux63~106 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.890 ns) 6.241 ns Mux63~107 4 COMB LC8_5_C2 1 " "Info: 4: + IC(1.039 ns) + CELL(0.890 ns) = 6.241 ns; Loc. = LC8_5_C2; Fanout = 1; COMB Node = 'Mux63~107'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.929 ns" { Mux63~106 Mux63~107 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.250 ns) + CELL(0.890 ns) 9.381 ns Mux63~109 5 COMB LC5_3_C1 1 " "Info: 5: + IC(2.250 ns) + CELL(0.890 ns) = 9.381 ns; Loc. = LC5_3_C1; Fanout = 1; COMB Node = 'Mux63~109'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.140 ns" { Mux63~107 Mux63~109 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.334 ns) + CELL(2.410 ns) 14.125 ns y\[0\] 6 PIN PIN_13 0 " "Info: 6: + IC(2.334 ns) + CELL(2.410 ns) = 14.125 ns; Loc. = PIN_13; Fanout = 0; PIN Node = 'y\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.744 ns" { Mux63~109 y[0] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.599 ns ( 39.64 % ) " "Info: Total cell delay = 5.599 ns ( 39.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.526 ns ( 60.36 % ) " "Info: Total interconnect delay = 8.526 ns ( 60.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.125 ns" { pc[0] Mux63~105 Mux63~106 Mux63~107 Mux63~109 y[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.125 ns" { pc[0] {} Mux63~105 {} Mux63~106 {} Mux63~107 {} Mux63~109 {} y[0] {} } { 0.000ns 2.650ns 0.253ns 1.039ns 2.250ns 2.334ns } { 0.161ns 0.890ns 0.358ns 0.890ns 0.890ns 2.410ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock pc[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} pc[0] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.125 ns" { pc[0] Mux63~105 Mux63~106 Mux63~107 Mux63~109 y[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.125 ns" { pc[0] {} Mux63~105 {} Mux63~106 {} Mux63~107 {} Mux63~109 {} y[0] {} } { 0.000ns 2.650ns 0.253ns 1.039ns 2.250ns 2.334ns } { 0.161ns 0.890ns 0.358ns 0.890ns 0.890ns 2.410ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "select_y\[1\] y\[10\] 14.434 ns Longest " "Info: Longest tpd from source pin \"select_y\[1\]\" to destination pin \"y\[10\]\" is 14.434 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns select_y\[1\] 1 PIN PIN_2 46 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_2; Fanout = 46; PIN Node = 'select_y\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { select_y[1] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.368 ns) + CELL(0.798 ns) 7.406 ns Mux53~128 2 COMB LC3_5_D1 1 " "Info: 2: + IC(5.368 ns) + CELL(0.798 ns) = 7.406 ns; Loc. = LC3_5_D1; Fanout = 1; COMB Node = 'Mux53~128'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.166 ns" { select_y[1] Mux53~128 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.890 ns) 8.556 ns Mux53~129 3 COMB LC1_5_D1 1 " "Info: 3: + IC(0.260 ns) + CELL(0.890 ns) = 8.556 ns; Loc. = LC1_5_D1; Fanout = 1; COMB Node = 'Mux53~129'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { Mux53~128 Mux53~129 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.281 ns) + CELL(0.358 ns) 9.195 ns Mux53~131 4 COMB LC2_5_D1 1 " "Info: 4: + IC(0.281 ns) + CELL(0.358 ns) = 9.195 ns; Loc. = LC2_5_D1; Fanout = 1; COMB Node = 'Mux53~131'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.639 ns" { Mux53~129 Mux53~131 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.260 ns) + CELL(0.879 ns) 10.334 ns Mux53~134 5 COMB LC3_4_D1 1 " "Info: 5: + IC(0.260 ns) + CELL(0.879 ns) = 10.334 ns; Loc. = LC3_4_D1; Fanout = 1; COMB Node = 'Mux53~134'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.139 ns" { Mux53~131 Mux53~134 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.610 ns) + CELL(2.490 ns) 14.434 ns y\[10\] 6 PIN PIN_113 0 " "Info: 6: + IC(1.610 ns) + CELL(2.490 ns) = 14.434 ns; Loc. = PIN_113; Fanout = 0; PIN Node = 'y\[10\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { Mux53~134 y[10] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.655 ns ( 46.11 % ) " "Info: Total cell delay = 6.655 ns ( 46.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.779 ns ( 53.89 % ) " "Info: Total interconnect delay = 7.779 ns ( 53.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.434 ns" { select_y[1] Mux53~128 Mux53~129 Mux53~131 Mux53~134 y[10] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.434 ns" { select_y[1] {} select_y[1]~out0 {} Mux53~128 {} Mux53~129 {} Mux53~131 {} Mux53~134 {} y[10] {} } { 0.000ns 0.000ns 5.368ns 0.260ns 0.281ns 0.260ns 1.610ns } { 0.000ns 1.240ns 0.798ns 0.890ns 0.358ns 0.879ns 2.490ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "id_ir\[7\] i_datain\[7\] clock -2.363 ns register " "Info: th for register \"id_ir\[7\]\" (data pin = \"i_datain\[7\]\", clock pin = \"clock\") is -2.363 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.673 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns id_ir\[7\] 2 REG LC4_1_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC4_1_A1; Fanout = 2; REG Node = 'id_ir\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { clock id_ir[7] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock id_ir[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} id_ir[7] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns i_datain\[7\] 1 PIN PIN_105 1 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_105; Fanout = 1; PIN Node = 'i_datain\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i_datain[7] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.081 ns) + CELL(0.079 ns) 4.400 ns id_ir\[7\] 2 REG LC4_1_A1 2 " "Info: 2: + IC(3.081 ns) + CELL(0.079 ns) = 4.400 ns; Loc. = LC4_1_A1; Fanout = 2; REG Node = 'id_ir\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.160 ns" { i_datain[7] id_ir[7] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 87 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 29.98 % ) " "Info: Total cell delay = 1.319 ns ( 29.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.081 ns ( 70.02 % ) " "Info: Total interconnect delay = 3.081 ns ( 70.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { i_datain[7] id_ir[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.400 ns" { i_datain[7] {} i_datain[7]~out0 {} id_ir[7] {} } { 0.000ns 0.000ns 3.081ns } { 0.000ns 1.240ns 0.079ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock id_ir[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} id_ir[7] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { i_datain[7] id_ir[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.400 ns" { i_datain[7] {} i_datain[7]~out0 {} id_ir[7] {} } { 0.000ns 0.000ns 3.081ns } { 0.000ns 1.240ns 0.079ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clock d_dataout\[1\] smdr1\[1\] 4.815 ns register " "Info: Minimum tco from clock \"clock\" to destination pin \"d_dataout\[1\]\" through register \"smdr1\[1\]\" is 4.815 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.663 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns smdr1\[1\] 2 REG LC3_1_E2 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC3_1_E2; Fanout = 1; REG Node = 'smdr1\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.773 ns" { clock smdr1[1] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock smdr1[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} smdr1[1] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 145 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.817 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.817 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns smdr1\[1\] 1 REG LC3_1_E2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC3_1_E2; Fanout = 1; REG Node = 'smdr1\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { smdr1[1] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(2.410 ns) 2.817 ns d_dataout\[1\] 2 PIN PIN_26 0 " "Info: 2: + IC(0.246 ns) + CELL(2.410 ns) = 2.817 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'd_dataout\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { smdr1[1] d_dataout[1] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.571 ns ( 91.27 % ) " "Info: Total cell delay = 2.571 ns ( 91.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.246 ns ( 8.73 % ) " "Info: Total interconnect delay = 0.246 ns ( 8.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.817 ns" { smdr1[1] d_dataout[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.817 ns" { smdr1[1] {} d_dataout[1] {} } { 0.000ns 0.246ns } { 0.161ns 2.410ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock smdr1[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} smdr1[1] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.817 ns" { smdr1[1] d_dataout[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.817 ns" { smdr1[1] {} d_dataout[1] {} } { 0.000ns 0.246ns } { 0.161ns 2.410ns } "" } }  } 0 0 "Minimum tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}