pcpu.tan.qmsg

可以实现CPU的VHDL源码

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register ex_ir\[11\] register zf 108.98 MHz 9.176 ns Internal " "Info: Clock \"clock\" has Internal fmax of 108.98 MHz between source register \"ex_ir\[11\]\" and destination register \"zf\" (period= 9.176 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.643 ns + Longest register register " "Info: + Longest register to register delay is 8.643 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns ex_ir\[11\] 1 REG LC8_6_A1 4 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC8_6_A1; Fanout = 4; REG Node = 'ex_ir\[11\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ex_ir[11] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.890 ns) 1.352 ns Decoder2~89 2 COMB LC4_6_A1 18 " "Info: 2: + IC(0.301 ns) + CELL(0.890 ns) = 1.352 ns; Loc. = LC4_6_A1; Fanout = 18; COMB Node = 'Decoder2~89'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.191 ns" { ex_ir[11] Decoder2~89 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 219 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.358 ns) 2.096 ns Add1~824 3 COMB LC6_6_A1 2 " "Info: 3: + IC(0.386 ns) + CELL(0.358 ns) = 2.096 ns; Loc. = LC6_6_A1; Fanout = 2; COMB Node = 'Add1~824'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.744 ns" { Decoder2~89 Add1~824 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(1.122 ns) 4.283 ns Add1~776 4 COMB LC5_8_A1 2 " "Info: 4: + IC(1.065 ns) + CELL(1.122 ns) = 4.283 ns; Loc. = LC5_8_A1; Fanout = 2; COMB Node = 'Add1~776'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.187 ns" { Add1~824 Add1~776 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 4.398 ns Add1~779 5 COMB LC6_8_A1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.115 ns) = 4.398 ns; Loc. = LC6_8_A1; Fanout = 2; COMB Node = 'Add1~779'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~776 Add1~779 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 4.513 ns Add1~782 6 COMB LC7_8_A1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.115 ns) = 4.513 ns; Loc. = LC7_8_A1; Fanout = 2; COMB Node = 'Add1~782'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~779 Add1~782 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 4.628 ns Add1~785 7 COMB LC8_8_A1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.115 ns) = 4.628 ns; Loc. = LC8_8_A1; Fanout = 2; COMB Node = 'Add1~785'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~782 Add1~785 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 4.743 ns Add1~788 8 COMB LC9_8_A1 2 " "Info: 8: + IC(0.000 ns) + CELL(0.115 ns) = 4.743 ns; Loc. = LC9_8_A1; Fanout = 2; COMB Node = 'Add1~788'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~785 Add1~788 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 4.858 ns Add1~791 9 COMB LC10_8_A1 2 " "Info: 9: + IC(0.000 ns) + CELL(0.115 ns) = 4.858 ns; Loc. = LC10_8_A1; Fanout = 2; COMB Node = 'Add1~791'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~788 Add1~791 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.115 ns) 5.458 ns Add1~794 10 COMB LC1_10_A1 2 " "Info: 10: + IC(0.485 ns) + CELL(0.115 ns) = 5.458 ns; Loc. = LC1_10_A1; Fanout = 2; COMB Node = 'Add1~794'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { Add1~791 Add1~794 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.573 ns Add1~800 11 COMB LC2_10_A1 2 " "Info: 11: + IC(0.000 ns) + CELL(0.115 ns) = 5.573 ns; Loc. = LC2_10_A1; Fanout = 2; COMB Node = 'Add1~800'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~794 Add1~800 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.688 ns Add1~803 12 COMB LC3_10_A1 2 " "Info: 12: + IC(0.000 ns) + CELL(0.115 ns) = 5.688 ns; Loc. = LC3_10_A1; Fanout = 2; COMB Node = 'Add1~803'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~800 Add1~803 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.803 ns Add1~806 13 COMB LC4_10_A1 2 " "Info: 13: + IC(0.000 ns) + CELL(0.115 ns) = 5.803 ns; Loc. = LC4_10_A1; Fanout = 2; COMB Node = 'Add1~806'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~803 Add1~806 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 5.918 ns Add1~809 14 COMB LC5_10_A1 2 " "Info: 14: + IC(0.000 ns) + CELL(0.115 ns) = 5.918 ns; Loc. = LC5_10_A1; Fanout = 2; COMB Node = 'Add1~809'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~806 Add1~809 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.115 ns) 6.033 ns Add1~812 15 COMB LC6_10_A1 2 " "Info: 15: + IC(0.000 ns) + CELL(0.115 ns) = 6.033 ns; Loc. = LC6_10_A1; Fanout = 2; COMB Node = 'Add1~812'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.115 ns" { Add1~809 Add1~812 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.668 ns) 6.701 ns Add1~814 16 COMB LC7_10_A1 2 " "Info: 16: + IC(0.000 ns) + CELL(0.668 ns) = 6.701 ns; Loc. = LC7_10_A1; Fanout = 2; COMB Node = 'Add1~814'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.668 ns" { Add1~812 Add1~814 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 223 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.277 ns) + CELL(0.798 ns) 7.776 ns Equal9~149 17 COMB LC10_10_A1 1 " "Info: 17: + IC(0.277 ns) + CELL(0.798 ns) = 7.776 ns; Loc. = LC10_10_A1; Fanout = 1; COMB Node = 'Equal9~149'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.075 ns" { Add1~814 Equal9~149 } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.600 ns) 8.643 ns zf 18 REG LC9_9_A1 2 " "Info: 18: + IC(0.267 ns) + CELL(0.600 ns) = 8.643 ns; Loc. = LC9_9_A1; Fanout = 2; REG Node = 'zf'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.867 ns" { Equal9~149 zf } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.862 ns ( 67.82 % ) " "Info: Total cell delay = 5.862 ns ( 67.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.781 ns ( 32.18 % ) " "Info: Total interconnect delay = 2.781 ns ( 32.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.643 ns" { ex_ir[11] Decoder2~89 Add1~824 Add1~776 Add1~779 Add1~782 Add1~785 Add1~788 Add1~791 Add1~794 Add1~800 Add1~803 Add1~806 Add1~809 Add1~812 Add1~814 Equal9~149 zf } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.643 ns" { ex_ir[11] {} Decoder2~89 {} Add1~824 {} Add1~776 {} Add1~779 {} Add1~782 {} Add1~785 {} Add1~788 {} Add1~791 {} Add1~794 {} Add1~800 {} Add1~803 {} Add1~806 {} Add1~809 {} Add1~812 {} Add1~814 {} Equal9~149 {} zf {} } { 0.000ns 0.301ns 0.386ns 1.065ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.485ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.277ns 0.267ns } { 0.161ns 0.890ns 0.358ns 1.122ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.668ns 0.798ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.673 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns zf 2 REG LC9_9_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC9_9_A1; Fanout = 2; REG Node = 'zf'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { clock zf } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock zf } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} zf {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 1.673 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns ex_ir\[11\] 2 REG LC8_6_A1 4 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC8_6_A1; Fanout = 4; REG Node = 'ex_ir\[11\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { clock ex_ir[11] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 110 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock ex_ir[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} ex_ir[11] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock zf } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} zf {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock ex_ir[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} ex_ir[11] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 110 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 41 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.643 ns" { ex_ir[11] Decoder2~89 Add1~824 Add1~776 Add1~779 Add1~782 Add1~785 Add1~788 Add1~791 Add1~794 Add1~800 Add1~803 Add1~806 Add1~809 Add1~812 Add1~814 Equal9~149 zf } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.643 ns" { ex_ir[11] {} Decoder2~89 {} Add1~824 {} Add1~776 {} Add1~779 {} Add1~782 {} Add1~785 {} Add1~788 {} Add1~791 {} Add1~794 {} Add1~800 {} Add1~803 {} Add1~806 {} Add1~809 {} Add1~812 {} Add1~814 {} Equal9~149 {} zf {} } { 0.000ns 0.301ns 0.386ns 1.065ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.485ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.277ns 0.267ns } { 0.161ns 0.890ns 0.358ns 1.122ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.115ns 0.668ns 0.798ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock zf } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} zf {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { clock ex_ir[11] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { clock {} clock~out0 {} ex_ir[11] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "reg_C1\[6\] d_datain\[6\] clock 5.193 ns register " "Info: tsu for register \"reg_C1\[6\]\" (data pin = \"d_datain\[6\]\", clock pin = \"clock\") is 5.193 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.658 ns + Longest pin register " "Info: + Longest pin to register delay is 6.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.310 ns) 1.310 ns d_datain\[6\] 1 PIN PIN_41 1 " "Info: 1: + IC(0.000 ns) + CELL(1.310 ns) = 1.310 ns; Loc. = PIN_41; Fanout = 1; PIN Node = 'd_datain\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d_datain[6] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.748 ns) + CELL(0.600 ns) 6.658 ns reg_C1\[6\] 2 REG LC6_1_C1 8 " "Info: 2: + IC(4.748 ns) + CELL(0.600 ns) = 6.658 ns; Loc. = LC6_1_C1; Fanout = 8; REG Node = 'reg_C1\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.348 ns" { d_datain[6] reg_C1[6] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 182 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.910 ns ( 28.69 % ) " "Info: Total cell delay = 1.910 ns ( 28.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.748 ns ( 71.31 % ) " "Info: Total interconnect delay = 4.748 ns ( 71.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.658 ns" { d_datain[6] reg_C1[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.658 ns" { d_datain[6] {} d_datain[6]~out0 {} reg_C1[6] {} } { 0.000ns 0.000ns 4.748ns } { 0.000ns 1.310ns 0.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 182 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 1.663 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clock 1 CLK PIN_95 260 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 260; CLK Node = 'clock'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns reg_C1\[6\] 2 REG LC6_1_C1 8 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC6_1_C1; Fanout = 8; REG Node = 'reg_C1\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.773 ns" { clock reg_C1[6] } "NODE_NAME" } } { "pcpu.v" "" { Text "D:/kevinquartusII/111/pcpu.v" 182 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock reg_C1[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} reg_C1[6] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.658 ns" { d_datain[6] reg_C1[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.658 ns" { d_datain[6] {} d_datain[6]~out0 {} reg_C1[6] {} } { 0.000ns 0.000ns 4.748ns } { 0.000ns 1.310ns 0.600ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { clock reg_C1[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { clock {} clock~out0 {} reg_C1[6] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}