counter.vhd

计数器的VHDL设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is 
port ( clk : in std_logic;
      reset: in std_logic;
      segH, segL : out std_logic_vector ( 7 downto 0));
end counter;

architecture counter of counter is 
signal cnt   : integer range 0 to 9999999;
signal cnt_h : integer range 0 to 9;
signal cnt_l : integer range 0 to 9;

-- calculatioin
begin 
	process (clk, reset)
	begin 
		if(reset='0') then 
			cnt<=0; 
			cnt_h<=0;
			cnt_l<=0;
		elsif (clk'event and clk='1') then
			if (cnt=9999999) then 
				cnt<=0;
				if (cnt_l=9) then
					cnt_l<=0;
					if(cnt_h=9) then
						cnt_h<=0;
					else cnt_h<=cnt_h+1;
					end if;
				else cnt_l<=cnt_l+1;
				end if;
			else cnt<=cnt+1;
			end if;
		end if;
	end process;

--display
	process (cnt_l, cnt_h)
	begin
		case cnt_l is
			when 0	=>		segL<="11111100";
			when 1	=>		segL<="01100000";
			when 2	=>		segL<="11011010";
			when 3	=>		segL<="11110010";
			when 4	=>		segL<="01100110";
			when 5	=>		segL<="10110110";
			when 6	=>		segL<="10111110";
			when 7	=>		segL<="11100000";
			when 8	=>		segL<="11111110";
			when 9	=>		segL<="11110110";
			when others =>  segL<="00000000";
		end case;
		
		case cnt_h is 
			when 0	=>		segH<="11111100";
			when 1	=>		segH<="01100000";
			when 2	=>		segH<="11011010";
			when 3	=>		segH<="11110010";
			when 4	=>		segH<="01100110";
			when 5	=>		segH<="10110110";
			when 6	=>		segH<="10111110";
			when 7	=>		segH<="11100000";
			when 8	=>		segH<="11111110";
			when 9	=>		segH<="11110110";
			when others =>  segH<="00000000";
		end case;
	end process;
end counter;