coregen.xml

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<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="disp_ram" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
disp_ram YourInstanceName (
    .addra(addra),
    .addrb(addrb),
    .clka(clka),
    .clkb(clkb),
    .dina(dina),
    .douta(douta),
    .doutb(doutb),
    .wea(wea));

 
		</Template>
		<Template label="textram" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
textram YourInstanceName (
    .addr(addr),
    .clk(clk),
    .din(din),
    .dout(dout),
    .we(we));

 
		</Template>
		<Template label="embedded_rom" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
embedded_rom YourInstanceName (
    .a(a),
    .clk(clk),
    .spo(spo));

 
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="disp_ram" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component disp_ram
    port (
    addra: IN std_logic_VECTOR(14 downto 0);
    addrb: IN std_logic_VECTOR(14 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dina: IN std_logic_VECTOR(7 downto 0);
    douta: OUT std_logic_VECTOR(7 downto 0);
    doutb: OUT std_logic_VECTOR(7 downto 0);
    wea: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : disp_ram
        port map (
            addra =&gt; addra,
            addrb =&gt; addrb,
            clka =&gt; clka,
            clkb =&gt; clkb,
            dina =&gt; dina,
            douta =&gt; douta,
            doutb =&gt; doutb,
            wea =&gt; wea);
 
		</Template>
		<Template label="textram" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component textram
    port (
    addr: IN std_logic_VECTOR(12 downto 0);
    clk: IN std_logic;
    din: IN std_logic_VECTOR(7 downto 0);
    dout: OUT std_logic_VECTOR(7 downto 0);
    we: IN std_logic);
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : textram
        port map (
            addr =&gt; addr,
            clk =&gt; clk,
            din =&gt; din,
            dout =&gt; dout,
            we =&gt; we);
 
		</Template>
		<Template label="embedded_rom" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component embedded_rom
    port (
    a: IN std_logic_VECTOR(7 downto 0);
    clk: IN std_logic;
    spo: OUT std_logic_VECTOR(7 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : embedded_rom
        port map (
            a =&gt; a,
            clk =&gt; clk,
            spo =&gt; spo);
 
		</Template>
	</Folder>
</RootFolder>