📄 d__modeltech_6.2b_xilinx_libs_unisim__info

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💻 2B_XILINX_LIBS_UNISIM__INFO
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dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L133707VImoL9]AEImznoU[5VOnLO1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufgmux_virtex4_vDP unisim vcomponents WFeZzdIJ9Y`oQcmg3TBHc0DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg cTZZ97QQ?M?JdFjILgiVh1DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgmux_virtex4 ImoL9]AEImznoU[5VOnLO1l133727L133720VJKlWbHWIJEEMmg;=W<2nJ0OE;C;6.2b;3531M7 ieee std_logic_1164M6 ieee std_logic_arithM5 unisim vpkgM4 std textioM3 ieee vital_timingM2 ieee vital_primitivesM1 unisim vcomponentso-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebufgpw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1552Vn2oO_Y725MG8cHf>WAm`k1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufgp_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgp n2oO_Y725MG8cHf>WAm`k1l1561L1560V9HeWjDFbgPY<dagSY0VF`0OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebufgsrw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127590V@S:i<84lJY8keJklG_=o`2OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufgsr_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgsr @S:i<84lJY8keJklG_=o`2l127599L127598VAHoBUSkc8e_<26GJZjHY@1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebufgtsw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127627VaH?NAed5Nl0DaZ`n_Sn5R0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufgts_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgts aH?NAed5Nl0DaZ`n_Sn5R0l127636L127635VWf2B@0=`7oGYYF=JU7zz11OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebufiow1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L133776VzR]k5ZRz2lglFo=6YIob`2OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufio_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufio zR]k5ZRz2lglFo=6YIob`2l133786L133785VzAFPk37[16nla8e@VI9am1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebufrw1157679452DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg cTZZ97QQ?M?JdFjILgiVh1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L133823Vz8U3UL_RmH9jM2:l_IKC23OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abufr_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg cTZZ97QQ?M?JdFjILgiVh1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufr z8U3UL_RmH9jM2:l_IKC23l133869L133841Vb@i6^U2T1gQN1>ahQ@fW03OE;C;6.2b;3531M5 ieee std_logic_1164M4 unisim vpkgM3 std textioM2 ieee vital_timingM1 ieee vital_primitiveso-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ebuftw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1589V7gML>K28Hg>11lBHX<`8A3OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Abuft_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work buft 7gML>K28Hg>11lBHX<`8A3l1599L1598V?EPOOblF:lOA5W1MWzYEj3OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_fpgacorew1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1650V8d0Z=62GQfCz[=78H`?>V2OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_fpgacore_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_fpgacore 8d0Z=62GQfCz[=78H`?>V2l1661L1660V<J6EU2O4LKbe[6D^z7zNi0OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_spartan2w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1691VhikKkW4RINaZjFk=:FO;?3OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_spartan2_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_spartan2 hikKkW4RINaZjFk=:FO;?3l1702L1701VdQiST<55g85Se:85@MQn61OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_spartan3w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1732V0BVLcPj[Y3nNla]cd@SC82OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_spartan3_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_spartan3 0BVLcPj[Y3nNla]cd@SC82l1743L1742Vn>jRSgj4`mJCDBgPj0`[K1OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_spartan3aw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L175567V`@lP9ABd[MG6EK]lY9=]<0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_spartan3a_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_spartan3a `@lP9ABd[MG6EK]lY9=]<0l175578L175577V4BgT3iXbK7eWTMf@KK?jK2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_virtexw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1774VaRY3Ia[mhaijP63JGCdnc0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_virtex_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex aRY3Ia[mhaijP63JGCdnc0l1785L1784Vja=JYY?2FS_B2i:6WEX]03OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_virtex2w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1816ViY]fY2e3cHhRWFE4BRYkK1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_virtex2_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex2 iY]fY2e3cHhRWFE4BRYkK1l1827L1826V7FeF02X6kXFa29ozoNEVc2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_virtex4w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L134087Vz@KJ1?>nEH>3=>jQ2aN`:2OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_virtex4_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex4 z@KJ1?>nEH>3=>jQ2aN`:2l134100L134098VcPjDIZiFcZ<5A@N84I^:o2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecapture_virtex5w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L156743VPH]TI2T9L]S1W8C?9W3hB3OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acapture_virtex5_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex5 PH]TI2T9L]S1W8C?9W3hB3l156756L156754VimffEHL3_<SEeDai5fjP41OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecarry4w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L156782V_1YHZZ>_L?04JIfGWj6cW1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acarry4_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work carry4 _1YHZZ>_L?04JIfGWj6cW1l156800L156796V2IH9@jlmlg4TJjD8B7Mcz2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Ecfglut5w1157679452DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg cTZZ97QQ?M?JdFjILgiVh1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L156857VBcF3_VVS<kLok7Ll07cA70OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Acfglut5_vDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg cTZZ97QQ?M?JdFjILgiVh1DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work cfglut5 BcF3_VVS<kLok7Ll07cA70l156885L156879VAV`Ra=JoV8UX_bmXTPSn43OE;C;6.2b;3531M5 ieee std_logic_1164M4 unisim vpkgM3 std textioM2 ieee vital_timingM1 ieee vital_primitiveso-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div10w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127664VhGIl^QFIhkGWAW`_V4ilA1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div10_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10 hGIl^QFIhkGWAW`_V4ilA1l127680L127676Vj];3`EaULf6Iz]aJRLY0E3OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div10rw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127724VhHmB?R;iIIj7Jk?P4Rcza0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div10r_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10r hHmB?R;iIIj7Jk?P4Rcza0l127742L127737VXG:^8ALjmDN?nWe;GX4051OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div10rsdw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127829VDb@25kA?;7EUnBjg0O6`n1OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div10rsd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10rsd Db@25kA?;7EUnBjg0O6`n1l127847L127842VzF9hATYVMccjOZMUka@R?2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div10sdw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L127940Ve>OXomJQ_gV9fh8QMM[4B3OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div10sd_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10sd e>OXomJQ_gV9fh8QMM[4B3l127957L127953VECbWTV_II?SZUVQaz2;cm0OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div12w1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L128013VcA[Pl?GbZK?@SUJ2f<8`j0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div12_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12 cA[Pl?GbZK?@SUJ2f<8`j0l128028L128024VXb14ELG[AY8O7eXTjlgaj2OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div12rw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L128071V0QR_ZB1Q0iJL:SfW3N9h`0OE;C;6.2b;3531o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Aclk_div12r_vDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12r 0QR_ZB1Q0iJL:SfW3N9h`0l128089L128084VD:CC6IYmi3[KEmQ]UmW^m3OE;C;6.2b;3531M1 ieee std_logic_1164o-source -93 -work d:\Modeltech_6.2b\xilinx_libs\unisimtExplicit 1Eclk_div12rsdw1157679452DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2dD:\Modeltech_6.2bFD:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0
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