avalonpwm.vhd

SOPC实验--Hello World实验:启动Quartus II软件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity AvalonPwm is
port(clk: in std_logic; --clk signal
wr_n:in std_logic; --write signal
addr:in std_logic; --address signal
WrData:in std_logic_vector(7 downto 0); --writedata signal
PwmOut:out std_logic); --Global signal
end AvalonPwm;

architecture one of AvalonPwm is
signal period:std_logic_vector(7 downto 0);
signal duty:std_logic_vector(7 downto 0);
signal counter:std_logic_vector(7 downto 0);
begin
process(clk,WrData)
begin
if rising_edge(clk) then
if (wr_n='0') then
if addr='0' then
period<=WrData;
duty<=duty;
else
period<=period;
duty<=WrData;
end if;
else
period<=period;
duty<=duty;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if counter=0 then counter<=period;
else counter<=counter-'1';
end if;
if counter>duty then PwmOut<='0';
else PwmOut<='1';
end if;
end if;
end process;
end one;