tb_read_ram.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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-- Company: 
-- Engineer:
--
-- Create Date:   14:52:14 02/19/2013
-- Design Name:   
-- Module Name:   D:/FpgaProgram/G510-106T/G510_106T_201302191436/tb_read_ram.vhd
-- Project Name:  G510_106T_1_1
-- Target Device:  
-- Tool versions:  
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_read_ram IS
END tb_read_ram;
 
ARCHITECTURE behavior OF tb_read_ram IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT read_ram3
    PORT(
         CLK : IN  std_logic;
         RAM3_RD_START : IN  std_logic;
         RAM3_ENB : OUT  std_logic;
         RAM3_ADDRB : OUT  std_logic_vector(10 downto 0);
         RAM3_ADDRB_REG : OUT  std_logic_vector(10 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal RAM3_RD_START : std_logic := '0';

 	--Outputs
   signal RAM3_ENB : std_logic;
   signal RAM3_ADDRB : std_logic_vector(10 downto 0);
   signal RAM3_ADDRB_REG : std_logic_vector(10 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: read_ram3 PORT MAP (
          CLK => CLK,
          RAM3_RD_START => RAM3_RD_START,
          RAM3_ENB => RAM3_ENB,
          RAM3_ADDRB => RAM3_ADDRB,
          RAM3_ADDRB_REG => RAM3_ADDRB_REG
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		RAM3_RD_START <= '0';
      wait for CLK_period*10;
		RAM3_RD_START <= '1';
      -- insert stimulus here 

      wait;
   end process;

END;