tb_g510_106a.vhd

来自「FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的」· VHDL 代码 · 共 2,139 行 · 第 1/5 页

VHD
2,139 行
字号
12345
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000000011";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000000100";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000000101";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000000110";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000000111";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000001000";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000001001";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000001010";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000001011";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
---manch------------------------------------------------------------------------
--------------------------------------------------------------------------------
			wait for CLK_period/8;
			wait for CLK_period*50;
			wait for CLK_period*10;			wait for CLK_period*16;			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period*8;--?---------------------------------1  "0110"----------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;-------------------------------2 "1001"-----------------------------------------------		--------------------------------------------------------------------------------			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;------------------------------3 "0110"------------------------------------------------	--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;-----------------------------4 "1001"---------------------------------------------------------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;----------------------------5 "01100"--------------------------------------------------	--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;----------------------------6 "0101"----------------------------------------------------------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0'; 			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;---------------------------7 "1010"---------------------------------------------------	--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;--1			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--------------------------------------------------------------------------------					MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';			wait for CLK_period;--0			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';			wait for CLK_period;			MANCHESTER_A <= '0';
			MANCHESTER_B <= '0';
			MANCHESTER_C <= '0';	
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--read manch
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
			wait for CLK_period*100;	
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110000";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110001";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110010";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110011";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110100";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110101";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			wait for CLK_period*50;	
			MANCHESTER_A <= '1';
			MANCHESTER_B <= '1';
			MANCHESTER_C <= '1';
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--read manch
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
			wait for CLK_period*100;	
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110000";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
			ARM_FRAME <= '1';			ARM_READ <= '1';
			ARM_ADDR <= "000000110001";
			wait for CLK_period*5;
			ARM_FRAME <= '0';			ARM_READ <= '0';
			wait for CLK_period*5;
--------------------------------------------------------------------------------
			ARM_FRAME <= '1';
12345

tb_g510_106a.vhd - 源码说明

本页面展示了「FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的」中的 tb_g510_106a.vhd 源码文件，采用 VHDL 编程语言编写，共 2,139 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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