📄 tb_g510_106a.vhd
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:42 12/29/2012
-- Design Name:
-- Module Name: D:/FpgaProgram/G510-106T/G510_106T_12_29/tb_G510_106T_1_1.vhd
-- Project Name: G510_106T_1_1
-- Target Device:
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.VComponents.all;
ENTITY tb_G510_106A IS
END tb_G510_106A;
ARCHITECTURE behavior OF tb_G510_106A IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT G510_106A
PORT(
CLK : IN std_logic;
ARM_RST : in std_logic;
CLK_ARM : in std_logic;
ARM_WRITE_OVER : in std_logic;
ARM_FRAME : IN std_logic;
ARM_WRITE : IN std_logic;
ARM_READ : IN std_logic;
ARM_ADDR : IN std_logic_vector(11 downto 0);
MANCHESTER_A : IN std_logic;
MANCHESTER_B : IN std_logic;
MANCHESTER_C : IN std_logic;
CODER_QEA_A : IN std_logic;
CODER_QEB_A : IN std_logic;
CODER_QEA_B : IN std_logic;
CODER_QEB_B : IN std_logic;
CODER_QEA_C : IN std_logic;
CODER_QEB_C : IN std_logic;
CODER_QEA_D : IN std_logic;
CODER_QEB_D : IN std_logic;
CODER_QEA_E : IN std_logic;
CODER_QEB_E : IN std_logic;
CODER_QEA_F : IN std_logic;
CODER_QEB_F : IN std_logic;
PULSE_OUT_EN : OUT std_logic_vector(15 downto 0);
PULSE_OUT_DIR : OUT std_logic_vector(15 downto 0);
PULSE_OUT : OUT std_logic_vector(15 downto 0);
-- PWM_OUT_en : OUT std_logic_vector(11 downto 0);
PWM_DIR_POSITIVE : OUT std_logic_vector(11 downto 0);
PWM_DIR_NEGATIVE : OUT std_logic_vector(11 downto 0);
PWM_OUT : OUT std_logic_vector(11 downto 0);
INTERRUPT_FOR_ARM : OUT std_logic;
-- Poa_add : out std_logic_vector(10 downto 0);-- Pod_data : out std_logic_vector(31 downto 0);
-- Poc_pul_reg : out std_logic_vector(15 downto 0);
-- Poc_p : out std_logic_vector(15 downto 0);
ARM_FPGA_DATA : INOUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal ARM_RST : std_logic;
signal CLK_ARM : std_logic := '0';
signal ARM_WRITE_OVER : std_logic := '0';
signal ARM_FRAME : std_logic := '0';
signal ARM_WRITE : std_logic := '0';
signal ARM_READ : std_logic := '0';
signal ARM_ADDR : std_logic_vector(11 downto 0) := (others => '0');
signal MANCHESTER_A : std_logic := '0';
signal MANCHESTER_B : std_logic := '0';
signal MANCHESTER_C : std_logic := '0';
signal CODER_QEA_A : std_logic := '0';
signal CODER_QEB_A : std_logic := '0';
signal CODER_QEA_B : std_logic := '0';
signal CODER_QEB_B : std_logic := '0';
signal CODER_QEA_C : std_logic := '0';
signal CODER_QEB_C : std_logic := '0';
signal CODER_QEA_D : std_logic := '0';
signal CODER_QEB_D : std_logic := '0';
signal CODER_QEA_E : std_logic := '0';
signal CODER_QEB_E : std_logic := '0';
signal CODER_QEA_F : std_logic := '0';
signal CODER_QEB_F : std_logic := '0';
--BiDirs
signal ARM_FPGA_DATA : std_logic_vector(15 downto 0);
--Outputs-- signal Pod_data : std_logic_vector(31 downto 0);
-- signal Poc_pul_reg : std_logic_vector(15 downto 0);
-- signal Poc_p : std_logic_vector(15 downto 0);
signal PULSE_OUT_EN : std_logic_vector(15 downto 0);
signal PULSE_OUT_DIR : std_logic_vector(15 downto 0);
signal PULSE_OUT : std_logic_vector(15 downto 0);
-- signal PWM_OUT_en : std_logic_vector(11 downto 0);
signal PWM_DIR_POSITIVE : std_logic_vector(11 downto 0);
signal PWM_DIR_NEGATIVE : std_logic_vector(11 downto 0);
signal PWM_OUT : std_logic_vector(11 downto 0);
signal INTERRUPT_FOR_ARM : std_logic;
-- Clock period definitions
constant CLK_period : time := 40 ns;
constant QEA_a_period : time := 800 ns;
constant QEB_a_period : time := 800 ns;
constant QEA_b_period : time := 800 ns; constant QEB_b_period : time := 800 ns;
constant QEA_c_period : time := 800 ns; constant QEB_c_period : time := 800 ns;
constant QEA_d_period : time := 800 ns; constant QEB_d_period : time := 800 ns;
constant QEA_e_period : time := 800 ns; constant QEB_e_period : time := 800 ns;
constant QEA_f_period : time := 800 ns; constant QEB_f_period : time := 800 ns;
constant CLK_ARM_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: G510_106A PORT MAP (
CLK => CLK,
ARM_RST => ARM_RST,
CLK_ARM => CLK_ARM,
ARM_WRITE_OVER => ARM_WRITE_OVER,
ARM_FRAME => ARM_FRAME,
ARM_WRITE => ARM_WRITE,
ARM_READ => ARM_READ,
ARM_ADDR => ARM_ADDR,
MANCHESTER_A => MANCHESTER_A,
MANCHESTER_B => MANCHESTER_B,
MANCHESTER_C => MANCHESTER_C,
CODER_QEA_A => CODER_QEA_A,
CODER_QEB_A => CODER_QEB_A,
CODER_QEA_B => CODER_QEA_B,
CODER_QEB_B => CODER_QEB_B,
CODER_QEA_C => CODER_QEA_C,
CODER_QEB_C => CODER_QEB_C,
CODER_QEA_D => CODER_QEA_D,
CODER_QEB_D => CODER_QEB_D,
CODER_QEA_E => CODER_QEA_E,
CODER_QEB_E => CODER_QEB_E,
CODER_QEA_F => CODER_QEA_F,
CODER_QEB_F => CODER_QEB_F,
PULSE_OUT_EN => PULSE_OUT_EN,
PULSE_OUT_DIR => PULSE_OUT_DIR,
PULSE_OUT => PULSE_OUT,
-- PWM_OUT_en => PWM_OUT_en,
PWM_DIR_POSITIVE => PWM_DIR_POSITIVE,
PWM_DIR_NEGATIVE => PWM_DIR_NEGATIVE,
PWM_OUT => PWM_OUT,
INTERRUPT_FOR_ARM => INTERRUPT_FOR_ARM,
-- Poa_add => Poa_add,
-- Pod_data => Pod_data,
-- Poc_pul_reg => Poc_pul_reg,
-- Poc_p => Poc_p,
ARM_FPGA_DATA => ARM_FPGA_DATA
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
QEA_a : process
begin
CODER_QEA_A <= '0';
wait for QEA_a_period/4;
CODER_QEA_A <= '1';
wait for QEA_a_period/2;
CODER_QEA_A <= '0';
wait for QEA_a_period/4;
end process;
QEB_a : process
begin
CODER_QEB_A <= '0';
wait for QEB_a_period/2;
CODER_QEB_A <= '1';
wait for QEB_a_period/2;
end process;
QEA_b : process
begin
CODER_QEA_B <= '0';
wait for QEA_b_period/4;
CODER_QEA_B <= '1';
wait for QEA_b_period/2;
CODER_QEA_B <= '0';
wait for QEA_b_period/4;
end process;
QEB_b : process
begin
CODER_QEB_B <= '0';
wait for QEB_b_period/2;
CODER_QEB_B <= '1';
wait for QEB_b_period/2;
end process;
QEA_c : process
begin
CODER_QEA_C <= '0';
wait for QEA_c_period/4;
CODER_QEA_C <= '1';
wait for QEA_c_period/2;
CODER_QEA_C <= '0';
wait for QEA_c_period/4;
end process;
QEB_c : process
begin
CODER_QEB_C <= '0';
wait for QEB_c_period/2;
CODER_QEB_C <= '1';
wait for QEB_c_period/2;
end process;
QEA_d : process
begin
CODER_QEA_D <= '0';
wait for QEA_d_period/4;
CODER_QEA_D <= '1';
wait for QEA_d_period/2;
CODER_QEA_D <= '0';
wait for QEA_d_period/4;
end process;
QEB_d : process
begin
CODER_QEB_D <= '0';
wait for QEB_d_period/2;
CODER_QEB_D <= '1';
wait for QEB_d_period/2;
end process;
QEA_e : process
begin
CODER_QEA_E <= '0';
wait for QEA_e_period/4;
CODER_QEA_E <= '1';
wait for QEA_e_period/2;
CODER_QEA_E <= '0';
wait for QEA_e_period/4;
end process;
QEB_e : process
begin
CODER_QEB_E <= '0';
wait for QEB_e_period/2;
CODER_QEB_E <= '1';
wait for QEB_e_period/2;
end process;
QEA_f : process
begin
CODER_QEA_F <= '0';
wait for QEA_f_period/4;
CODER_QEA_F <= '1';
wait for QEA_f_period/2;
CODER_QEA_F <= '0';
wait for QEA_f_period/4;
end process;
QEB_f : process
begin
CODER_QEB_F <= '0';
wait for QEB_f_period/2;
CODER_QEB_F <= '1';
wait for QEB_f_period/2;
end process;
CLKarm : process
begin
CLK_ARM <= '0';
wait for CLK_ARM_period/2;
CLK_ARM <= '1';
wait for CLK_ARM_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
--init
ARM_RST <= '0';
ARM_WRITE_OVER <= '0';
ARM_FRAME <= '0';
ARM_WRITE <= '0';
ARM_READ <= '0';
ARM_ADDR <= "000000000000";
wait for CLK_period*50000;
--------------------------------------------------------------------------------
MANCHESTER_A <= '0';
MANCHESTER_B <= '0';
MANCHESTER_C <= '0';
ARM_ADDR <= "011111111111";--2047
--------------------------------------------------------------------------------
wait for CLK_period*10;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------WRITE--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------pulse_1 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1;--2048 ARM_FPGA_DATA <= "0000000000000000";--100 wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_2 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_3 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000010"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_4 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000011"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_5 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000100"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_6 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000101"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5;--------------------------------------------------------------------------------pulse_7 ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000000000110"; wait for CLK_period*5; ARM_FRAME <= '0'; ARM_WRITE <= '0'; wait for CLK_period*5; ARM_FRAME <= '1'; ARM_WRITE <= '1'; ARM_ADDR <= ARM_ADDR + 1; ARM_FPGA_DATA <= "0000000100000001";⌨️ 快捷键说明
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