read_sram.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 		Han'slaser
-- Engineer: 		Zhouj110624
-- Create Date:    08:53:15 10/22/2012 
-- Design Name: 	read_sram
-- Module Name:    read_sram - Behavioral 
-- Project Name: 	Top_fpga
-- Target Devices: 
--功能说明：用于FPGA从SRAM中读取数据，从SRAM中读取数据时，分两次读取，高16位和低16位，	
--并送至脉冲发生模块和PWM模块中
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----------------------------------------------------------------------------------
entity read_ram3 is	
	port(
		CLK				: in	std_logic;
--		RST				: in	std_logic;
		RAM3_RD_START	: in	std_logic;
		RAM3_ENB			: out	std_logic;
		RAM3_ADDRB		: out	std_logic_vector(10 downto 0);
		RAM3_ADDRB_REG	: out	std_logic_vector(10 downto 0)
		);
end read_ram3;
----------------------------------------------------------------------------------
architecture Behavioral of read_ram3 is
----------------------------------------------------------------------------------
	signal rd_addr				:	std_logic_vector(10 downto 0) := (others=>'0');
	signal rd_start_reg1		:	std_logic := '0';
	signal rd_start_reg2		:	std_logic := '0';
	signal rd_en				:	std_logic := '0';
	signal rd_end 				:	std_logic := '0';

begin
	
	RAM3_ADDRB	<= rd_addr;
	
	Pr_D	:	
	process(CLK)
	begin
		if rising_edge(CLK) then				
			rd_start_reg1		<= RAM3_RD_START;
			rd_start_reg2		<= rd_start_reg1;
			RAM3_ADDRB_REG		<= rd_addr;
		end if;
	end process;
			
	Pr_en	:	
	process(CLK)
	begin
		if rising_edge(CLK) then	
			if rd_start_reg1 = '1' and rd_start_reg2 = '0' then
				rd_en		<= '1';
			elsif rd_end = '1' then
				rd_en		<= '0';
			else
				null;
			end if;
		end if;
	end process;
				
	Pr_add	:	
	process(Clk)
	begin
		if rising_edge(Clk) then
			if (rd_en = '0') then	
				RAM3_ENB <= '0';
				rd_end <= '0';
				rd_addr <= "01111111111";
			else
				if rd_addr < "10001000000" then
					RAM3_ENB <= '1';
					rd_end <= '0';
					rd_addr <= rd_addr + 1;
				else
					RAM3_ENB <= '0';	
					rd_end <= '1';								
				end if;
			end if;
		end if;
	end process;

end Behavioral;