pulse_generation.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 		Hans'laser
-- Engineer: 		Zhouj110624
-- Create Date:   	14:48:31 09/11/2012 
-- Design Name: 	Pulse_generation
-- Module Name:   	Pulse_generation - Behavioral 
-- Project Name: 	Pulse_generation
-- Target Devices:	xc3s500e-4f256
-- 功能说明	：	脉冲信号发生器，以1ms作为输出的时间单位，1ms输出的脉冲数目为PULSE_NUM。
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity Pulse_generation is
    Port ( 	
			CLK 				: in  STD_LOGIC;
			RST				: in	std_logic;
			INTERRUPT_IN	: in	std_logic;
			PULSE_NUM		: in	std_logic_vector(15 downto 0);--输入1ms时间内应输出的脉冲数目值
			PULSE_OUT 		: out STD_LOGIC);--电机驱动器脉冲信号，对于步进电机来说：最大值为200KHz，脉宽不小于2.5us
end Pulse_generation;

architecture Behavioral of Pulse_generation is
-----------------------------------小数分频---------------------------------------
	component delet_contr is
		Port ( 	
				CLK 		   	: in  STD_LOGIC;
				RST  				: in	std_logic;
				INTERRUPT_IN	: in	std_logic;
				PULSE_NUM 		: in  std_logic_vector(15 downto 0);
				PULSE_OUT 		: out STD_LOGIC);
	end component;
------------------------------------2分频-----------------------------------------
	component divide_freq is
		 Port ( CLK 		: in  STD_LOGIC;
				  RST  		: in	std_logic;
				  PULSE_IN	: in	std_logic;
				  CLK_OUT 	: out STD_LOGIC);
	end component;
------------------------------------信号------------------------------------------
	signal pulse_reg	:	std_logic := '0';--小数分频输出脉冲信号
	----------------------------------------------------------------------------------
--	signal CLK_100M_num	:	std_logic_vector(17 downto 0) := "000000000000001101";--1ms时间内100MHz时钟脉冲个数
--	signal CLK_100M_num	:	std_logic_vector(17 downto 0) := "000100111000100000";--时间脉冲数
--	signal Sbd_pul_num	:	std_logic_vector(14 downto 0) := "000000000000101";--1ms时间内输出脉冲个数
begin			

----------------------------------------------------------------------------------
	Inst_delet_contr	:	delet_contr	
	port map(
			CLK				=>	CLK,
			RST				=>	RST,
			INTERRUPT_IN	=>	INTERRUPT_IN,
			PULSE_NUM		=>	PULSE_NUM,
			PULSE_OUT		=>	pulse_reg
			);
----------------------------------------------------------------------------------
	Inst_divide_freq_2	:	divide_freq	
	port map(
			CLK			=>	CLK,
			RST			=>	RST,
			PULSE_IN		=>	pulse_reg,
			CLK_OUT		=>	PULSE_OUT
			);
----------------------------------------------------------------------------------										
end Behavioral;