delet_contr.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

 ----------------------------------------------------------------------------------
-- Company: Han's laser
-- Engineer: Zhouj110624
-- Create Date:    16:44:34 08/21/2012 
-- Module Name:    delet_contr - Behavioral 
-- Project Name:  divi_freq_fo
-- Target Devices: xc3s500e-4f256
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity delet_contr is
    Port (
			  CLK 			: in  STD_LOGIC;
			  RST				:	in	std_logic;
			  INTERRUPT_IN	:	in	std_logic;
           PULSE_NUM 	: in  std_logic_vector(15 downto 0);
           PULSE_OUT		: out  STD_LOGIC);
end delet_contr;

architecture Behavioral of delet_contr is

signal now_state,next_state : std_logic_vector(4 downto 0) := "00001";
constant idle		:	std_logic_vector(4 downto 0) := "00001";
constant waiting	:	std_logic_vector(4 downto 0) := "00010";
constant	getva		:	std_logic_vector(4 downto 0) := "00100";
constant output_1	:	std_logic_vector(4 downto 0) := "01000";
constant output_2	:	std_logic_vector(4 downto 0) := "10000";

signal delete_signal	:	std_logic := '1';
signal Sbc_en_1	:	std_logic := '0';
signal Sbc_en_2	:	std_logic := '0';
signal pulse_num_2	:	std_logic_vector(16 downto 0) := ( others => '0' );

begin

--	PULSE_OUT	<=	CLK or delete_signal;--或运算，删除脉冲
	process(CLK)
	begin
		if rising_edge(CLK) then
			if delete_signal = '1' then
				PULSE_OUT <= '1';
			else
				PULSE_OUT <= '0';
			end if;
		end if;
	end process;
----------------------------------------------------------------------------------
--小数分频算法进程，输入时钟脉冲：CLK_num;输出信号脉冲：PULSE_NUM;
----------------------------------------------------------------------------------
	process(CLK)
	variable count : std_logic_vector(16 downto 0) :=( others => '0' );
	begin
		if rising_edge(CLK) then 
			if RST = '1' then
				count := ( others => '0' );
				delete_signal <= '1';
			else
				if Sbc_en_1 = '1' and Sbc_en_2 = '0' then 
					count := ( others => '0' );
					delete_signal <= '0';
				elsif Sbc_en_1 = '0' and Sbc_en_2 = '0' then
					count := ( others => '0' );
					delete_signal <= '1';
				elsif Sbc_en_1 = '1' and Sbc_en_2 = '1' then
					count := count + pulse_num_2;--计数值加上输出脉冲值
					--计数值小于等于时钟脉冲，则输出删除信号
					if count < "11000011010100000"  then
--						count := count + PULSE_NUM;--计数值加上输出脉冲值				
						delete_signal <= '1';
					--计数值大于时钟脉冲，则不输出删除信号，且计数值减去时钟脉冲值
					else 
						count := count - "11000011010100000";
						delete_signal <= '0';
					end if;
				else
					count := ( others => '0' );
					delete_signal <= '1';
				end if;
			end if;
		end if;
	end process; 
----------------------------------------------------------------------------------
--
----------------------------------------------------------------------------------
Pr_reg	:	process(CLK)
				begin
					if rising_edge(CLK) then
						now_state <= next_state;
					end if;
				end process;
				
Pr_com	:	process(RST,now_state,INTERRUPT_IN)
				begin
					if RST = '1' then
						next_state <= idle;
					else
					case now_state is
						when idle	=>
							if INTERRUPT_IN = '1' then
								next_state <= waiting;
							else
								next_state <= idle;
							end if;
						when waiting	=>
							if INTERRUPT_IN = '0' then
								next_state <= getva;
							else
								next_state <= waiting;
							end if;
						when getva	=>	
							next_state <= output_1;
						when output_1	=>	
							if INTERRUPT_IN = '1' then
								next_state <= output_2;
							else
								next_state <= output_1; 
							end if;
						when output_2	=>
							if INTERRUPT_IN = '0' then
								next_state <= getva;
							else
								next_state <= output_2;
							end if;
						when others	=>	next_state <= idle;
					end case;
					end if;
				end process;
				
Pr_output	:	process(CLK)
					begin
						if rising_edge(CLK) then
							case now_state is
								when idle 		=> 
									Sbc_en_1 <= '0';
									Sbc_en_2 <= '0';
									pulse_num_2 <= ( others => '0' );
								when waiting	=>	
									Sbc_en_1 <= '0';
									Sbc_en_2 <= '0';
									pulse_num_2 <= ( others => '0' );
								when getva		=>	
									pulse_num_2 <= PULSE_NUM & '0';
									if PULSE_NUM = "0000000000000000" then
										Sbc_en_1 <= '1';
										Sbc_en_2 <= '1';
									else
										Sbc_en_1 <= '1';
										Sbc_en_2 <= '0';
									end if;
								when output_1	=>	
									Sbc_en_1 <= '1';
									Sbc_en_2 <= '1';
								when output_2	=>	
									Sbc_en_1 <= '1';
									Sbc_en_2 <= '1';
								when others 	=> 
									Sbc_en_1 <= '0';
									Sbc_en_2 <= '0';
									pulse_num_2 <= ( others => '0' );
							end case;
						end if; 
					end process;
end Behavioral;