pwm.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 			han'slaser
-- Engineer:  			Zhouj110624
-- Create Date:    	11:39:44 09/24/2012 
-- Design Name: 		pwm
-- Module Name:    	pwm - Behavioral 
-- Project Name: 		pwm_12
-- Target Devices: 
-- 功能说明：PWM信号发生器，频率和占空比可分别通过FREQUENCY_NUM和DUTY_NUM调节
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity pwm is
    Port ( 	
			CLK 				: 	in	STD_LOGIC;
			RST				:	in	std_logic;
			CLK_10MHz		:	in	std_logic;
			PWM_OUT_EN		:	in	std_logic;
			FREQUENCY_NUM	:	in	std_logic_vector(15 downto 0);
			DUTY_NUM 		: 	in  STD_LOGIC_VECTOR (13 downto 0);
			PWM_OUT 			: 	out STD_LOGIC
		);
end pwm;
----------------------------------------------------------------------------------
architecture Behavioral of pwm is

signal pwm_out_reg	:	std_logic := '0';	
signal cnt				:	std_logic_vector(16 downto 0) := (others => '0');

begin

	PWM_OUT <= pwm_out_reg;

----------------------------------------------------------------------------------
--PWM频率调节进程，对时钟计数
----------------------------------------------------------------------------------
	Pr_cnt	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				cnt <= (others => '0');
			else
				if CLK_10MHz = '1' then
					if cnt < FREQUENCY_NUM - 1 then--20KHz
						cnt <= cnt + 1;
					else
						cnt <= (others => '0');
					end if;
				else
					null;
				end if;
			end if;
		end if;
	end process;
	
----------------------------------------------------------------------------------
--PWM占空比调节进程，将输入占空比值与时钟计数值进行比较
----------------------------------------------------------------------------------		
	Pr_comp	:	
	process(CLK)
	begin	
		if rising_edge(CLK) then
			if PWM_OUT_EN = '0' then 
				pwm_out_reg <= '0';
			else
				if CLK_10MHz = '1' then
					if cnt(13 downto 0) < DUTY_NUM  then	
						pwm_out_reg <= '1';
					else
						pwm_out_reg <= '0';
					end if;
				else
					null;
				end if;
			end if;
		end if;
	end process;

end Behavioral;