write_coder.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 		Han'slaser
-- Engineer: 		Zhouj110624
-- Create Date:    08:53:15 12/17/2012 
-- Design Name: 	Write_coder
-- Module Name:    Write_coder - Behavioral 
-- Project Name: 	Top_fpga
-- Target Devices: 
--功能说明：用于连接曼彻斯特解码和SRAM模块，将曼彻斯特码解码数据拆分成两个16位数据，	
--再写入SRAM中
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----------------------------------------------------------------------------------
entity Write_coder is
	port(
		CLK						: in	std_logic;
		RST						: in	std_logic;
		CODER_CNT_A				: in	std_logic_vector(31 downto 0);--编码器脉冲计数值输入
		CODER_CNT_B				: in	std_logic_vector(31 downto 0);
		CODER_CNT_C				: in	std_logic_vector(31 downto 0);
		CODER_CNT_D				: in	std_logic_vector(31 downto 0);--编码器脉冲计数值输入
		CODER_CNT_E				: in	std_logic_vector(31 downto 0);
		CODER_CNT_F				: in	std_logic_vector(31 downto 0);
		FPGA_WRITE_RAM2_ADDR	: out std_logic_vector(10 downto 0);--输出fpga写sram地址
		FPGA_WRITE_RAM2_DATE	: out std_logic_vector(31 downto 0)--输出fpga写sram数据
		);
end Write_coder;

architecture Behavioral of Write_coder is

	signal ram_addr_reg					:	std_logic_vector(2 downto 0) := (others => '0');
	signal coder_cnt_a_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal coder_cnt_b_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal coder_cnt_c_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal coder_cnt_d_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal coder_cnt_e_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal coder_cnt_f_reg				:	std_logic_vector(31 downto 0) := (others => '0');

begin

	FPGA_WRITE_RAM2_ADDR	<= "00000000" & ram_addr_reg;
	coder_cnt_a_reg 		<=	CODER_CNT_A(15 downto 0) & CODER_CNT_A(31 downto 16);
	coder_cnt_b_reg 		<=	CODER_CNT_B(15 downto 0) & CODER_CNT_B(31 downto 16);
	coder_cnt_c_reg 		<=	CODER_CNT_C(15 downto 0) & CODER_CNT_C(31 downto 16);
	coder_cnt_d_reg 		<=	CODER_CNT_D(15 downto 0) & CODER_CNT_D(31 downto 16);
	coder_cnt_e_reg 		<=	CODER_CNT_E(15 downto 0) & CODER_CNT_E(31 downto 16);
	coder_cnt_f_reg 		<=	CODER_CNT_F(15 downto 0) & CODER_CNT_F(31 downto 16);
	
----------------------------------------------------------------------------------
--get ram2 addr
----------------------------------------------------------------------------------	
		
	Pr_addr	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				ram_addr_reg <= "000";
			else
				if ram_addr_reg < "101" then
					ram_addr_reg <= ram_addr_reg + 1;
				else
					ram_addr_reg <= "000";
				end if;
			end if;
		end if;
	end process;
				
----------------------------------------------------------------------------------
--get ram2 data
----------------------------------------------------------------------------------

	FPGA_WRITE_RAM2_DATE	<=	coder_cnt_a_reg when ram_addr_reg = "000" else
									coder_cnt_b_reg when ram_addr_reg = "001" else
									coder_cnt_c_reg when ram_addr_reg = "010" else
									coder_cnt_d_reg when ram_addr_reg = "011" else
									coder_cnt_e_reg when ram_addr_reg = "100" else
									coder_cnt_f_reg when ram_addr_reg = "101" else
									(others => '0');
												
					
end Behavioral;