write_sensor.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 		Han'slaser
-- Engineer: 		Zhouj110624
-- Create Date:    08:53:15 12/17/2012 
-- Design Name: 	Write_sensor
-- Module Name:    Write_sensor - Behavioral 
-- Project Name: 	Top_fpga
-- Target Devices: 
--功能说明：用于连接曼彻斯特解码和SRAM模块，将曼彻斯特码解码数据拆分成两个16位数据，	
--再写入SRAM中
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
----------------------------------------------------------------------------------

entity Write_sensor is 
	port(
		CLK						:	in	std_logic;
		RST						:	in	std_logic;
		DECODE_DATE_A			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		DECODE_DATE_B			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		DECODE_DATE_C			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		FPGA_WRITE_RAM1_ADDR	:	out std_logic_vector(10 downto 0);--输出fpga写sram地址
		FPGA_WRITE_RAM1_DATE	:	out std_logic_vector(31 downto 0)--输出fpga写sram数据
		);
end Write_sensor;
		
architecture Behavioral of Write_sensor is

	signal ram_addr_reg					:	std_logic_vector(5 downto 0) := (others => '0');
	constant edition_num					:	std_logic_vector(31 downto 0) := x"0100000C";--01.00.00.12
	constant alter_data					:	std_logic_vector(31 downto 0) := x"07DD0418";--20130424
	signal edition_num_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal alter_data_reg				:	std_logic_vector(31 downto 0) := (others => '0');
	signal decode_data_a_reg			:	std_logic_vector(31 downto 0) := (others => '0');
	signal decode_data_b_reg			:	std_logic_vector(31 downto 0) := (others => '0');
	signal decode_data_c_reg			:	std_logic_vector(31 downto 0) := (others => '0');
	
begin

	FPGA_WRITE_RAM1_ADDR <= "00000" & ram_addr_reg;
	edition_num_reg		<=	edition_num(15 downto 0) & edition_num(31 downto 16);
	alter_data_reg			<=	alter_data(15 downto 0) & alter_data(31 downto 16);
	decode_data_a_reg		<= DECODE_DATE_A(15 downto 0) & DECODE_DATE_A(31 downto 16);
	decode_data_b_reg		<= DECODE_DATE_B(15 downto 0) & DECODE_DATE_B(31 downto 16);
	decode_data_c_reg		<= DECODE_DATE_C(15 downto 0) & DECODE_DATE_C(31 downto 16);

----------------------------------------------------------------------------------
--get ram1 add
----------------------------------------------------------------------------------		
	
	Pr_add	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				ram_addr_reg <= "011000";
			else
				if ram_addr_reg < "100001" then 
					ram_addr_reg <= ram_addr_reg + 1;
				else
					ram_addr_reg <= "011000";
				end if;
			end if;
		end if;
	end process;
			
----------------------------------------------------------------------------------
--get ram1 data
----------------------------------------------------------------------------------

	FPGA_WRITE_RAM1_DATE	<=	decode_data_a_reg when ram_addr_reg = "011000" else
									decode_data_b_reg when ram_addr_reg = "011001" else
									decode_data_c_reg when ram_addr_reg = "011010" else
									edition_num_reg 	when ram_addr_reg = "100000" else
									alter_data_reg   	when ram_addr_reg = "100001" else
									(others => '0');
							
							
end Behavioral;