system_rst.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:04:17 01/31/2013 
-- Design Name: 
-- Module Name:    System_rst - Behavioral 
-- Project Name: 

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity System_rst is
    Port ( 
				CLK			: in	std_logic;
--				LOCKED_OUT	: in	std_logic;
				ARM_RST 		: in	STD_LOGIC;
				SYS_RST 		: out STD_LOGIC
			);
end System_rst;

architecture Behavioral of System_rst is

	signal rst_reg		: std_logic := '0';
	signal rst_reg1	: std_logic := '0';
	signal rst_reg2	: std_logic := '0';
	signal count_rst	: std_logic := '0';	
	signal cnt			: std_logic_vector(11 downto 0) := (others=>'0');

begin

	Pr_count	:
	process(ClK)
	begin
--		if LOCKED_OUT = '0' then
--			cnt			<= (others=>'0');
--			count_rst	<= '0';
		if rising_edge(CLK) then
			if cnt < 4095 then
				cnt			<= cnt + 1;
				count_rst	<= '1';
			else
				count_rst <= '0';
			end if;
		end if;
	end process;
				
	rst_reg	<=	 count_rst or ARM_RST;
							
	Pr_D	:
	process(Clk)
	begin
		if rising_Edge(Clk) then
			rst_reg1		<= rst_reg;
			rst_reg2 	<= rst_reg1 and rst_reg;
			SYS_RST		<= rst_reg2 and rst_reg1;
		end if;
	end process;					
					
end Behavioral;