📄 pulse_16.vhd
字号:
----------------------------------------------------------------------------------
-- Company: Han's laser
-- Engineer: Zhouj110624
-- Create Date: 16:44:34 11/26/2012
-- Module Name: Pulse_16 - Behavioral
-- Project Name: Pulse_16
-- Target Devices: xc3s500e-4f256
-- 功能说明：产生16路脉冲信号，以1ms作为输出的时间单位，1ms输出的脉冲数目为PULSE_DATA_IN。
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Pulse_16 is
port(
CLK : in std_logic;
RST : in std_logic;
INTERRUPT_IN : in std_logic;
PULSE_DATA_IN : in std_logic_vector(31 downto 0);--输入脉冲数据，高16位为脉冲数目数据，低16位为地址、使能和方向。
CHANNEL_ADDR : in std_logic_vector(10 downto 0);
PULSE_EN : out std_logic_vector(15 downto 0);--输出16路使能信号
PULSE_DIR : out std_logic_vector(15 downto 0);--输出16路方向信号
PULSE_OUT : out std_logic_vector(15 downto 0)--输出16路脉冲信号
);
end Pulse_16;
----------------------------------------------------------------------------------
architecture Behavioral of Pulse_16 is
component Pulse_generation is
Port (
CLK : in STD_LOGIC;
RST : in std_logic;
INTERRUPT_IN : in std_logic;
PULSE_NUM : in std_logic_vector(15 downto 0);--输入1ms时间内应输出的脉冲数目值
PULSE_OUT : out STD_LOGIC);--电机驱动器脉冲信号，对于步进电机来说：最大值为200KHz，脉宽不小于2.5us
end component;
----------------------------------------------------------------------------------
signal channel_en : std_logic := '0';
signal channel_en_reg : std_logic_vector(15 downto 0) := ( others => '0' );signal channel_dir : std_logic := '0';signal channel_dir_reg : std_logic_vector(15 downto 0) := ( others => '0' );
signal channel_addr_reg : std_logic_vector(10 downto 0) := ( others => '0' );--电机通道地址
----------------------------------------------------------------------------------
signal pulse_num_reg : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_1 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_2 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_3 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_4 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_5 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_6 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_7 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_8 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_9 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_10 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_11 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_12 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_13 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_14 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_15 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_num_reg_16 : std_logic_vector(15 downto 0) := ( others => '0' );
signal pulse_reg : std_logic_vector(15 downto 0) := ( others => '1' );
----------------------------------------------------------------------------------
begin
PULSE_EN <= channel_en_reg;
PULSE_DIR <= channel_dir_reg;
Pr_out :
process(CLK)
begin
if rising_edge(CLK) then
PULSE_OUT <= pulse_reg;
end if;
end process;
----------------------------------------------------------------------------------
--输入数据类型判断，Sbc_input_en不为‘0’，不接收输入数据
----------------------------------------------------------------------------------
Pr_in :
process(CLK)
begin
if rising_edge(CLK) then
-- if RST = '1' then-- pulse_num_reg <= ( others => '0' );-- channel_addr_reg <= ( others => '0' );-- channel_en <= '0';-- channel_dir <= '0';-- else
if CHANNEL_ADDR(10 downto 4) = "1000000" and (PULSE_DATA_IN(31 downto 25) = "0000000" ) and (PULSE_DATA_IN(23 downto 17) = "0000000" ) then
-- if CHANNEL_ADDR(10 downto 4) = "1000000" then
pulse_num_reg <= PULSE_DATA_IN(15 downto 0);
channel_addr_reg <= CHANNEL_ADDR(10 downto 0);
channel_en <= PULSE_DATA_IN( 24 );
channel_dir <= PULSE_DATA_IN( 16 );
else
null;
end if;
-- end if;
end if;
end process;
----------------------------------------------------------------------------------
--通道地址判断
----------------------------------------------------------------------------------
Pr_judge :
process(CLK)
begin
if rising_edge(CLK) then
case channel_addr_reg is
when "10000000000" =>
channel_en_reg(0) <= channel_en;
channel_dir_reg(0) <= channel_dir;
pulse_num_reg_1 <= pulse_num_reg;
when "10000000001" =>
channel_en_reg(1) <= channel_en;
channel_dir_reg(1) <= channel_dir;
pulse_num_reg_2 <= pulse_num_reg;
when "10000000010" =>
channel_en_reg(2) <= channel_en;
channel_dir_reg(2) <= channel_dir;
pulse_num_reg_3 <= pulse_num_reg;
when "10000000011" =>
channel_en_reg(3) <= channel_en;
channel_dir_reg(3) <= channel_dir;
pulse_num_reg_4 <= pulse_num_reg;
when "10000000100" =>
channel_en_reg(4) <= channel_en;
channel_dir_reg(4) <= channel_dir;
pulse_num_reg_5 <= pulse_num_reg;
when "10000000101" =>
channel_en_reg(5) <= channel_en;
channel_dir_reg(5) <= channel_dir;
pulse_num_reg_6 <= pulse_num_reg;
when "10000000110" =>
channel_en_reg(6) <= channel_en;
channel_dir_reg(6) <= channel_dir;
pulse_num_reg_7 <= pulse_num_reg;
when "10000000111" =>
channel_en_reg(7) <= channel_en;
channel_dir_reg(7) <= channel_dir;
pulse_num_reg_8 <= pulse_num_reg;
when "10000001000" =>
channel_en_reg(8) <= channel_en;
channel_dir_reg(8) <= channel_dir;
pulse_num_reg_9 <= pulse_num_reg;
when "10000001001" =>
channel_en_reg(9) <= channel_en;
channel_dir_reg(9) <= channel_dir;
pulse_num_reg_10 <= pulse_num_reg;
when "10000001010" =>
channel_en_reg(10) <= channel_en;
channel_dir_reg(10) <= channel_dir;
pulse_num_reg_11 <= pulse_num_reg;
when "10000001011" =>
channel_en_reg(11) <= channel_en;
channel_dir_reg(11) <= channel_dir;
pulse_num_reg_12 <= pulse_num_reg;
when "10000001100" =>
channel_en_reg(12) <= channel_en;
channel_dir_reg(12) <= channel_dir;
pulse_num_reg_13 <= pulse_num_reg;
when "10000001101" =>
channel_en_reg(13) <= channel_en;
channel_dir_reg(13) <= channel_dir;
pulse_num_reg_14 <= pulse_num_reg;
when "10000001110" =>
channel_en_reg(14) <= channel_en;
channel_dir_reg(14) <= channel_dir;
pulse_num_reg_15 <= pulse_num_reg;
when "10000001111" =>
channel_en_reg(15) <= channel_en;
channel_dir_reg(15) <= channel_dir;
pulse_num_reg_16 <= pulse_num_reg;
when others => null;
end case;
end if;
end process;
----------------------------------------------------------------------------------
--16路脉冲信号发生器例化
----------------------------------------------------------------------------------
Inst_pulse_1 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_1,
PULSE_OUT => pulse_reg(0)
);
Inst_pulse_2 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_2,
PULSE_OUT => pulse_reg(1)
);
Inst_pulse_3 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_3,
PULSE_OUT => pulse_reg(2)
);
Inst_pulse_4 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_4,
PULSE_OUT => pulse_reg(3)
);
Inst_pulse_5 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_5,
PULSE_OUT => pulse_reg(4)
);
Inst_pulse_6 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_6,
PULSE_OUT => pulse_reg(5)
);
Inst_pulse_7 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_7,
PULSE_OUT => pulse_reg(6)
);
Inst_pulse_8 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_8,
PULSE_OUT => pulse_reg(7)
);
Inst_pulse_9 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_9,
PULSE_OUT => pulse_reg(8)
);
Inst_pulse_10 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_10,
PULSE_OUT => pulse_reg(9)
);
Inst_pulse_11 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_11,
PULSE_OUT => pulse_reg(10)
);
Inst_pulse_12 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_12,
PULSE_OUT => pulse_reg(11)
);
Inst_pulse_13 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_13,
PULSE_OUT => pulse_reg(12)
);
Inst_pulse_14 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_14,
PULSE_OUT => pulse_reg(13)
);
Inst_pulse_15 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_15,
PULSE_OUT => pulse_reg(14)
);
Inst_pulse_16 : Pulse_generation
port map(
CLK => CLK,
RST => RST,
INTERRUPT_IN => INTERRUPT_IN,
PULSE_NUM => pulse_num_reg_16,
PULSE_OUT => pulse_reg(15)
);
----------------------------------------------------------------------------------
end Behavioral;⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -