codr_rst.vhd

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity Coder_rst is 
	port(
		CLK						: in	std_logic;
		RST						: in	std_logic;
		CHANNEL_ADDR			: in	std_logic_vector(10 downto 0);
		CODER_RST_DATA_IN		: in	std_logic_vector(31 downto 0);
		CODER_RST_DATA_OUT	: out	std_logic_vector(5 downto 0)
		);
end Coder_rst;

architecture Behavioral of Coder_rst is

begin
		
	Pr_in	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				CODER_RST_DATA_OUT <= ( others => '0' );
			else
				if CHANNEL_ADDR(10 downto 0) = "10001000000" and CODER_RST_DATA_IN(31 downto 22) = "0000000000" and CODER_RST_DATA_IN(15 downto 0) = "0000000000000000"then
					CODER_RST_DATA_OUT <= CODER_RST_DATA_IN( 21 downto 16 );
				else
					null;
				end if;
			end if;
		end if;
	end process;
	
end Behavioral;