c30fd5619124f031c5a130300f4ee5aabb7bd9df.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 			Han'slaser
-- Engineer:  			Zhouj110624
-- Create Date:    	16:29:22 10/08/2012 
-- Design Name: 		decoding_crc
-- Module Name:    	decoding_crc - Behavioral 
-- Project Name: 		decoding_crc
-- Target Devices: 	XC2C128
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity decoding_crc is
    Port ( 
			CLK 			: in  STD_LOGIC;
			RST			: in	std_logic;
         MANCHESTER	: in  STD_LOGIC;
         DECODE_DATA : out STD_LOGIC_VECTOR (31 downto 0)
		  );
end decoding_crc;
---------------------------------------------------------------------------------- 
architecture Behavioral of decoding_crc is
----------------------------------------------------------------------------------
	component decoding is
		 Port ( CLK									: in  STD_LOGIC;
				  DECODE_EN							: in  STD_LOGIC;
				  MANCHESTER_WITHOUT_HEADER	: in  STD_LOGIC;	--输入的曼切斯特码
				  DECODE_ERROR						: out	STD_LOGIC;
				  DECODE_OUT						: out std_logic_vector( 20 downto 0)	--解码后的串行编码
				);
	end component;
----------------------------------------------------------------------------------			  
	component decod_state is
		 Port ( CLK 								: in  STD_LOGIC;
				  RST									: in	std_logic;
				  DECODE_ERROR						: in	STD_LOGIC;
				  MANCHESTER						: in 	STD_LOGIC;	--输入含同步头的曼切斯特码
				  DETECTION							: out std_logic;
				  MANCHESTER_WITHOUT_HEADER	: out STD_LOGIC;	--去除同步头后的曼切斯特码
				  DECODE_EN		 					: out STD_LOGIC	--编码使能输出
				 );
	end component;
----------------------------------------------------------------------------------
	signal manchester_without_head	: std_logic := '0';
	signal decode_en						: std_logic := '0';
	signal detection						: std_logic := '0';
	signal decode_error					: std_logic := '0';
	signal decode_out						: std_logic_vector(20 downto 0) := (others => '0');
	
begin
	
	DECODE_DATA		<= detection & "0000000000" & decode_out;
----------------------------------------------------------------------------------	
	Inst_mystate	:	decod_state
		port map(
					CLK								=> CLK,
					RST								=>	RST,
					DECODE_ERROR					=>	decode_error,
					MANCHESTER						=> MANCHESTER,
					DETECTION						=>	detection,
					MANCHESTER_WITHOUT_HEADER	=>	manchester_without_head,
					DECODE_EN						=>	decode_en
					);
----------------------------------------------------------------------------------											
	Inst_decoding	:	decoding
		port map(
					CLK								=>	CLK,
					DECODE_EN						=>	decode_en,
					MANCHESTER_WITHOUT_HEADER	=>	manchester_without_head,
					DECODE_ERROR					=>	decode_error,
					DECODE_OUT						=> decode_out
					);
----------------------------------------------------------------------------------
end Behavioral;