ff2e0105c4204411092dea0e415201ac0bc821f9.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

            <spirit:configurableElementValue spirit:referenceId="parameter_port_a_write_rate">50</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_algorithm">Minimum_Area</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_fill_remaining_memory_locations">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_ecctype">No_ECC</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_port_b_clock">100</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_use_error_injection_pins">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_port_a_clock">100</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_read_width_a">32</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_read_width_b">16</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_reset_type">SYNC</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_register_porta_output_of_memory_primitives">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_register_portb_output_of_softecc">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_port_b_enable_rate">100</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_output_reset_value_a">0</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_output_reset_value_b">0</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_load_init_file">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_register_portb_output_of_memory_core">false</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_coe_file">no_coe_file_loaded</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_error_injection_type">Single_Bit_Error_Injection</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_collision_warnings">ALL</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_reset_priority_a">CE</spirit:configurableElementValue>
            <spirit:configurableElementValue spirit:referenceId="parameter_reset_priority_b">CE</spirit:configurableElementValue>
         </spirit:configurableElementValues>
         <spirit:vendorExtensions>
            <xilinx:instanceProperties>
             <xilinx:projectOptions>
               <xilinx:projectName>coregen</xilinx:projectName>
               <xilinx:outputDirectory>./</xilinx:outputDirectory>
               <xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
               <xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
             </xilinx:projectOptions>
             <xilinx:part>
               <xilinx:device>xc3s500e</xilinx:device>
               <xilinx:deviceFamily>spartan3e</xilinx:deviceFamily>
               <xilinx:package>ft256</xilinx:package>
               <xilinx:speedGrade>-4</xilinx:speedGrade>
             </xilinx:part>
             <xilinx:flowOptions>
               <xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
               <xilinx:designEntry>VHDL</xilinx:designEntry>
               <xilinx:asySymbol>true</xilinx:asySymbol>
               <xilinx:flowVendor>Foundation_ISE</xilinx:flowVendor>
               <xilinx:addPads>false</xilinx:addPads>
               <xilinx:removeRPMs>false</xilinx:removeRPMs>
               <xilinx:createNDF>false</xilinx:createNDF>
               <xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
               <xilinx:formalVerification>false</xilinx:formalVerification>
             </xilinx:flowOptions>
             <xilinx:simulationOptions>
               <xilinx:simulationModel>Behavioral</xilinx:simulationModel>
               <xilinx:simulationLanguage>VHDL_and_Verilog</xilinx:simulationLanguage>
               <xilinx:foundationSym>false</xilinx:foundationSym>
             </xilinx:simulationOptions>
           </xilinx:instanceProperties>
            <xilinx:generationHistory>
               <xilinx:fileSet>
                  <xilinx:name>customization_generator</xilinx:name>
               </xilinx:fileSet>
               <xilinx:fileSet>
                  <xilinx:name>ip_xco_generator</xilinx:name>
                  <xilinx:file>
                     <xilinx:name>./sram.xco</xilinx:name>
                     <xilinx:userFileType>xco</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:49:46 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x2C5CED0E</xilinx:checkSum>
                  </xilinx:file>
               </xilinx:fileSet>
               <xilinx:fileSet>
                  <xilinx:name>implementation_netlist_generator</xilinx:name>
                  <xilinx:file>
                     <xilinx:name>./blk_mem_gen_ds512.pdf</xilinx:name>
                     <xilinx:userFileType>pdf</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0xFF542E99</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./blk_mem_gen_readme.txt</xilinx:name>
                     <xilinx:userFileType>txt</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0xED96AB8B</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.asy</xilinx:name>
                     <xilinx:userFileType>asy</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:49:48 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0xB95DA5B8</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.ngc</xilinx:name>
                     <xilinx:userFileType>ngc</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:40 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x7905ACC3</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.sym</xilinx:name>
                     <xilinx:userFileType>asy</xilinx:userFileType>
                     <xilinx:userFileType>unknown</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:31 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x1179B466</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.v</xilinx:name>
                     <xilinx:userFileType>verilog</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x7C75F256</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.veo</xilinx:name>
                     <xilinx:userFileType>veo</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0xD54FC567</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.vhd</xilinx:name>
                     <xilinx:userFileType>vhdl</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x488D44BB</xilinx:checkSum>
                  </xilinx:file>
                  <xilinx:file>
                     <xilinx:name>./sram.vho</xilinx:name>
                     <xilinx:userFileType>vho</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:30 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x0CA284C7</xilinx:checkSum>
                  </xilinx:file>
               </xilinx:fileSet>
               <xilinx:fileSet>
                  <xilinx:name>instantiation_template_generator</xilinx:name>
               </xilinx:fileSet>
               <xilinx:fileSet>
                  <xilinx:name>xco_generator</xilinx:name>
                  <xilinx:file>
                     <xilinx:name>./sram.xco</xilinx:name>
                     <xilinx:userFileType>xco</xilinx:userFileType>
                     <xilinx:timeStamp>Wed Jan 30 07:50:46 GMT 2013</xilinx:timeStamp>
                     <xilinx:checkSum>0x6163B458</xilinx:checkSum>