5eb92698f827db0550b355682f87fe721c23724e.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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-- Company: 
-- Engineer:
--
-- Create Date:   16:00:04 01/30/2013
-- Design Name:   
-- Module Name:   D:/FpgaProgram/G510-106T/G510_106T_add_201301301548/tb_write_sensor.vhd
-- Project Name:  G510_106T_1_1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Write_sensor
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_write_sensor IS
END tb_write_sensor;
 
ARCHITECTURE behavior OF tb_write_sensor IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Write_sensor
    PORT(
         Clk : IN  std_logic;
         Pic_Decod_a : IN  std_logic_vector(31 downto 0);
         Pic_Decod_b : IN  std_logic_vector(31 downto 0);
         Pic_Decod_c : IN  std_logic_vector(31 downto 0);
         Poa_fpga_wr : OUT  std_logic_vector(10 downto 0);
         Pod_decod : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Pic_Decod_a : std_logic_vector(31 downto 0) := (others => '0');
   signal Pic_Decod_b : std_logic_vector(31 downto 0) := (others => '0');
   signal Pic_Decod_c : std_logic_vector(31 downto 0) := (others => '0');

 	--Outputs
   signal Poa_fpga_wr : std_logic_vector(10 downto 0);
   signal Pod_decod : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Write_sensor PORT MAP (
          Clk => Clk,
          Pic_Decod_a => Pic_Decod_a,
          Pic_Decod_b => Pic_Decod_b,
          Pic_Decod_c => Pic_Decod_c,
          Poa_fpga_wr => Poa_fpga_wr,
          Pod_decod => Pod_decod
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for Clk_period*10;
		Pic_Decod_a <= "01010101010101011010101010101010";
		Pic_Decod_b <= "11001100001100111000100000010001";
		Pic_Decod_c <= "00100010000100011110111000110011";
      -- insert stimulus here 

      wait;
   end process;

END;