4ae43a2e684f58b1d178e55193fa3308f674432f.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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-- Company: 
-- Engineer:
--
-- Create Date:   13:56:12 01/31/2013
-- Design Name:   
-- Module Name:   D:/FpgaProgram/G510-106T/G510_106T_add_201301311000/testbench/Tb_System_rst.vhd
-- Project Name:  G510_106T_1_1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: System_rst
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Tb_System_rst IS
END Tb_System_rst;
 
ARCHITECTURE behavior OF Tb_System_rst IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT System_rst
    PORT(
         Clk : IN  std_logic;
         Pic_arm_rst : IN  std_logic;
         Poc_sys_rst : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal Clk : std_logic := '0';
   signal Pic_arm_rst : std_logic := '0';

 	--Outputs
   signal Poc_sys_rst : std_logic;

   -- Clock period definitions
   constant Clk_period : time := 40 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: System_rst PORT MAP (
          Clk => Clk,
          Pic_arm_rst => Pic_arm_rst,
          Poc_sys_rst => Poc_sys_rst
        );

   -- Clock process definitions
   Clk_process :process
   begin
		Clk <= '0';
		wait for Clk_period/2;
		Clk <= '1';
		wait for Clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		wait for Clk_period*10000;
		Pic_arm_rst <= '0';
      wait for Clk_period*100;
		Pic_arm_rst <= '1';
		wait for Clk_period*10;
		Pic_arm_rst <= '0';
      -- insert stimulus here 

      wait;
   end process;

END;