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📄 063e8efbca3031257e9eab90c72bc80eb94c5192.svn-base

📁 FPGA与ARM EPI通信,控制16路步进电机和12路DC马达 VHDL编写的
💻 SVN-BASE
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">  <header>    <!-- ISE source project file created by Project Navigator.             -->    <!--                                                                   -->    <!-- This file contains project source information including a list of -->    <!-- project source files, project and process properties.  This file, -->    <!-- along with the project source files, is sufficient to open and    -->    <!-- implement in ISE Project Navigator.                               -->    <!--                                                                   -->    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->  </header>  <version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>  <files>    <file xil_pn:name="sram.ngc" xil_pn:type="FILE_NGC">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="sram.v" xil_pn:type="FILE_VERILOG">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>      <association xil_pn:name="PostMapSimulation"/>      <association xil_pn:name="PostRouteSimulation"/>      <association xil_pn:name="PostTranslateSimulation"/>    </file>    <file xil_pn:name="sram.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>      <association xil_pn:name="PostMapSimulation"/>      <association xil_pn:name="PostRouteSimulation"/>      <association xil_pn:name="PostTranslateSimulation"/>    </file>  </files>  <properties>    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>    <property xil_pn:name="Device" xil_pn:value="xc3s500e" xil_pn:valueState="non-default"/>    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sram|sram_a" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top File" xil_pn:value="sram.vhd" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sram" xil_pn:valueState="non-default"/>    <property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/>    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>    <!--                                                                                  -->    <!-- The following properties are for internal use only. These should not be modified.-->    <!--                                                                                  -->    <property xil_pn:name="PROP_DesignName" xil_pn:value="sram" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-01-30T15:50:49" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="552A56EEF46647959A60E4EDF73D28EC" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>  </properties>  <bindings/>  <libraries/>  <autoManagedFiles>    <!-- The following files are identified by `include statements in verilog -->    <!-- source files and are automatically managed by Project Navigator.     -->    <!--                                                                      -->    <!-- Do not hand-edit this section, as it will be overwritten when the    -->    <!-- project is analyzed based on files automatically identified as       -->    <!-- include files.                                                       -->  </autoManagedFiles></project>

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