0a79538c4ad5a85eb8050e20c094edffde9a5937.svn-base

来自「FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的」· SVN-BASE 代码 · 共 96 行

----------------------------------------------------------------------------------
-- Company: 			han'slaser
-- Engineer:  			Zhouj110624
-- Create Date:    	11:39:44 09/24/2012 
-- Design Name: 		pwm
-- Module Name:    	pwm - Behavioral 
-- Project Name: 		pwm_12
-- Target Devices: 
-- 功能说明：1KHz
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity interrupt is
    Port ( 	
			CLK 				: 	in	STD_LOGIC;
			RST 				:	in	std_logic;
			INTERRUPT_OUT 	: 	out STD_LOGIC
		);
end interrupt;
----------------------------------------------------------------------------------
architecture Behavioral of interrupt is

signal interrupt_reg	:	std_logic := '0';	
signal CLK_100KHz		:	std_logic := '0';
signal divide_cnt		:	std_logic_vector(7 downto 0) := (others => '0');
signal cnt				:	std_logic_vector(6 downto 0) := (others => '0');
begin
	INTERRUPT_OUT <= interrupt_reg;
----------------------------------------------------------------------------------
--分频进程，由25MHz分至500KHz
----------------------------------------------------------------------------------
Pr_div	:	process(CLK)
				begin	
					if rising_edge(CLK) then 
						if RST = '1' then
							divide_cnt <= (others => '0');
							CLK_100KHz <= '0';
						else
							if divide_cnt < "11111000" then--248
								divide_cnt <=divide_cnt + 1;
								CLK_100KHz <= '0';
							elsif  divide_cnt = "11111000" then--248
								CLK_100KHz <= '1';
								divide_cnt <=divide_cnt + 1;
							else
								divide_cnt <= (others => '0');
								CLK_100KHz <= '0';
							end if;
						end if;
					end if;
				end process;
----------------------------------------------------------------------------------
--PWM频率调节进程，对时钟计数
----------------------------------------------------------------------------------
Pr_cnt	:	process(CLK)
				begin
					if rising_edge(CLK) then
						if RST = '1' then
							cnt <= (others => '0');
						else
							if CLK_100KHz = '1' then
								if cnt < "1100011" then--20KHz
									cnt <= cnt + 1;
								else
									cnt <= (others => '0');
								end if;
							else
								null;
							end if;
						end if;
					end if;
				end process;
----------------------------------------------------------------------------------
--PWM占空比调节进程，将输入占空比值与时钟计数值进行比较
----------------------------------------------------------------------------------		
Pr_comp	:	process(CLK)
				begin	
					if rising_edge(CLK) then
						if CLK_100KHz = '1' then
							if cnt < "1010000"  then	
								interrupt_reg <= '1';
							else
								interrupt_reg <= '0';
							end if;
						else
							null;
						end if;
					end if;
				end process;

end Behavioral;