11f00f63e4d089227807eb4b84c310d6cab4fe80.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

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-- Company: Han's laser
-- Engineer: Zhouj110624
-- Create Date:    14:02:09 08/03/2012 
-- Module Name:    divide_freq - Behavioral 
-- Project Name:  divi_freq_fo
-- Target Devices: xc3s500e-4f256
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

entity divide_freq is
    Port ( CLK 		: in  STD_LOGIC;
			  RST			: in	std_logic;
			  PULSE_IN	: in	std_logic;
           CLK_OUT 	: out STD_LOGIC);
end divide_freq;

architecture Behavioral of divide_freq is

signal CLK_reg	:	std_logic :='1';

begin

	CLK_OUT <= CLK_reg;
	
	Pr_out	:	
	process(CLK)
	begin
		if rising_edge(CLK) then
			if RST = '1' then
				CLK_reg <= '1';
			else
				if PULSE_IN = '0' then
					CLK_reg <= not CLK_reg;
				else
					null;
				end if;
			end if;
		end if;
	end process;
end Behavioral;