1110d61dfd5744217107d8060759577bdc0831ab.svn-base

FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的

----------------------------------------------------------------------------------
-- Company: 		Han'slaser
-- Engineer: 		Zhouj110624
-- Create Date:    	17:28:25 10/16/2012 
-- Design Name:		ARM_FPGA 
-- Module Name:    	ARM_EPI - Behavioral 
-- Project Name: 	ARM_FPGA
-- Target Devices: 	
-- 说明：ARM芯片LM3S9B92的EPI接口通用模式时序，与FPGA进行通信

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;

entity ARM_EPI is
    Port ( 	
			CLK 				: in		std_logic;--ARM EPI接口传输时钟
			ARM_FRAME 		: in  	STD_LOGIC;--帧
			ARM_WRITE 		: in  	STD_LOGIC;--ARM向FPGA中写
			ARM_READ 		: in  	STD_LOGIC;--ARM从FPGA中读				
			ARM_ADDR 		: in  	STD_LOGIC_VECTOR (11 downto 0);--ARM送读写地址
			SENSOR_DATA		: in  	std_logic_vector(15 downto 0);
			CODER_DATA		: in  	std_logic_vector(15 downto 0);
			RAM3_WEA			: out		std_logic_vector(0 downto 0);
			RAM1_ENB			: out 	std_logic;
			RAM2_ENB			: out 	std_logic;
			RAM3_DINA		: out 	std_logic_vector(15 downto 0);
			RAM3_ADDRA		: out 	std_logic_vector(11 downto 0);
			RAM12_ADDRA		: out 	std_logic_vector(11 downto 0);
			ARM_FPGA_DATA	: inout 	STD_LOGIC_VECTOR (15 downto 0));--ARM与FPGA通信双向口
end ARM_EPI;

architecture Behavioral of ARM_EPI is

	signal arm_write_reg_1	:	std_logic := '0';
	signal arm_write_reg_2	:	std_logic := '0';
	signal arm_frame_reg		:	std_logic := '0';
	signal arm1_read_reg		:	std_logic := '0';
	signal arm2_read_reg		:	std_logic := '0';

begin

----------------------------------------------------------------------------------
--Read from FPGA ram 
----------------------------------------------------------------------------------
	RAM12_ADDRA			<= ARM_ADDR;
	ARM_FPGA_DATA		<= SENSOR_DATA when ( arm1_read_reg = '1' ) else
								CODER_DATA 	when ( arm2_read_reg = '1' ) else
								(others => 'Z');
  	arm1_read_reg		<= ARM_READ  when ( ( ARM_ADDR >= "000000110000" ) and ( ARM_ADDR < "000001000100" ) ) else
							'0';
	arm2_read_reg		<= ARM_READ  when ( ARM_ADDR < "000000110000" )  else
							'0';
	RAM1_ENB		<= arm1_read_reg;
	RAM2_ENB		<= arm2_read_reg;
	
----------------------------------------------------------------------------------
--register output
----------------------------------------------------------------------------------
--	Pr_output	:
--	process(CLK)
--	begin
--		if 
-------End---------------------------------------------------------------------------

-------------------------------------------------------------------------------------
--	Write to FPGA ram
-------------------------------------------------------------------------------------

	Pr_D_1	:	
	process(CLK)
		begin
			if rising_edge(CLK)	then
				arm_write_reg_2 	<= ARM_WRITE;
				arm_write_reg_1	<= arm_write_reg_2;
				arm_frame_reg 		<= ARM_FRAME;
				RAM3_WEA(0) 		<= arm_write_reg_1 and arm_frame_reg;
			end if;
		end process;
	
	Pr_1	:	
	process(CLK)
		begin
			if rising_edge(CLK) then
				RAM3_DINA 	<= ARM_FPGA_DATA;
				RAM3_ADDRA 	<= ARM_ADDR;
			end if;
		end process;
				
-------End---------------------------------------------------------------------------

end Behavioral;