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📄 f94f50a030cad7600ace279f9decb7baf66f5bfe.svn-base

📁 FPGA与ARM EPI通信,控制16路步进电机和12路DC马达 VHDL编写的
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">  <header>    <!-- ISE source project file created by Project Navigator.             -->    <!--                                                                   -->    <!-- This file contains project source information including a list of -->    <!-- project source files, project and process properties.  This file, -->    <!-- along with the project source files, is sufficient to open and    -->    <!-- implement in ISE Project Navigator.                               -->    <!--                                                                   -->    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->  </header>  <version xil_pn:ise_version="12.4" xil_pn:schema_version="2"/>  <files>    <file xil_pn:name="../source/vhd/ARM_EPI.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/Codr_rst.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/decod_state.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/decoding.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/decoding_crc.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/delet_contr.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/divide_freq.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/interrupt.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/PCK_CRC8_D1.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/Pulse_16.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/Pulse_generation.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/pwm.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/pwm_12.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/Write_coder.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="ipcore_dir/my_dcm.xaw" xil_pn:type="FILE_XAW">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="ipcore_dir/sram.xco" xil_pn:type="FILE_COREGEN">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/Write_sensor.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="ipcore_dir/ram_3.xco" xil_pn:type="FILE_COREGEN">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/testbench/tb_pwm_12.vhd" xil_pn:type="FILE_VHDL"/>    <file xil_pn:name="../source/testbench/tb_write_sensor.vhd" xil_pn:type="FILE_VHDL"/>    <file xil_pn:name="../source/testbench/tb_write_coder.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="PostMapSimulation"/>      <association xil_pn:name="PostRouteSimulation"/>      <association xil_pn:name="PostTranslateSimulation"/>    </file>    <file xil_pn:name="../source/testbench/Tb_System_rst.vhd" xil_pn:type="FILE_VHDL"/>    <file xil_pn:name="../source/vhd/G510_106A.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/System_rst.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/read_sram.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/log_filter.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/vhd/quad_encoder.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/ucf/G510_106A.ucf" xil_pn:type="FILE_UCF">      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="../source/testbench/tb_G510_106A.vhd" xil_pn:type="FILE_VHDL">      <association xil_pn:name="BehavioralSimulation"/>      <association xil_pn:name="PostMapSimulation"/>      <association xil_pn:name="PostRouteSimulation"/>      <association xil_pn:name="PostTranslateSimulation"/>    </file>    <file xil_pn:name="ipcore_dir/sram.xise" xil_pn:type="FILE_COREGENISE">      <association xil_pn:name="Implementation"/>    </file>    <file xil_pn:name="ipcore_dir/ram_3.xise" xil_pn:type="FILE_COREGENISE">      <association xil_pn:name="Implementation"/>    </file>  </files>  <autoManagedFiles>    <!-- The following files are identified by `include statements in verilog -->    <!-- source files and are automatically managed by Project Navigator.     -->    <!--                                                                      -->    <!-- Do not hand-edit this section, as it will be overwritten when the    -->    <!-- project is analyzed based on files automatically identified as       -->    <!-- include files.                                                       -->  </autoManagedFiles>  <properties>    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>

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