📄 dfbc94567928dc8a62ce75cb7b66fb2dd347da47.svn-base
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signal ram3_dina : std_logic_vector(15 downto 0) := ( others => '0' );
signal ram12_addrb : std_logic_vector(11 downto 0) := ( others => '0' );
--sram<->read_sram----------------------------------------------------------------
signal ram3_read : std_logic := '0';
signal ram3_addrb : std_logic_vector(10 downto 0) := ( others => '0' );
signal ram3_doutb : std_logic_vector(31 downto 0) := ( others => '0' );
--read_sram->pulse_16\pwm_12\interrupt\Coder_rst----------------------------------
signal channel_addr : std_logic_vector(10 downto 0) := ( others => '0' );
--Coder_rst->Coder_detec----------------------------------------------------------
signal coder_rst_num : std_logic_vector(5 downto 0) := ( others => '0' );
--interrupt->read_sram------------------------------------------------------------
signal interrupt_for_arm_reg : std_logic := '0';
--others--------------------------------------------------------------------------
signal ram_en : std_logic_vector(0 downto 0) := "1";
signal ram12_ena : std_logic := '1';
signal coder_a_rst : std_logic := '0';
signal coder_b_rst : std_logic := '0';
signal coder_c_rst : std_logic := '0';
signal coder_d_rst : std_logic := '0';
signal coder_e_rst : std_logic := '0';
signal coder_f_rst : std_logic := '0';
begin
ram12_ena <= '1';
ram_en <= "1";
INTERRUPT_FOR_ARM <= interrupt_for_arm_reg;
coder_a_rst <= coder_rst_num(0);
coder_b_rst <= coder_rst_num(1);
coder_c_rst <= coder_rst_num(2);
coder_d_rst <= coder_rst_num(3);
coder_e_rst <= coder_rst_num(4);
coder_f_rst <= coder_rst_num(5);
----------------------------------------------------------------------------------
--元件例化
----------------------------------------------------------------------------------
Inst_System_rst : System_rst
port map(
CLK => CLK_25M,
-- LOCKED_OUT => LOCKED_OUT,
ARM_RST => ARM_RST,
SYS_RST => sys_rst
);
----------------------------------------------------------------------------------
Inst_my_dcm : my_dcm
port map( CLKIN_IN => CLK,
RST_IN => DCM_RST, CLKFX_OUT => CLK_100M,-- CLKIN_IBUFG_OUT => , CLK0_OUT => CLK_25M, CLK2X_OUT => CLK_50M );
----------------------------------------------------------------------------------
Inst_decoding_crc_1 : decoding_crc
port map(
CLK => CLK_100M,
RST => sys_rst,
MANCHESTER => MANCHESTER_A,
DECODE_DATA => sensor_temp_a
);
----------------------------------------------------------------------------------
Inst_decoding_crc_2 : decoding_crc
port map(
CLK => CLK_100M,
RST => sys_rst,
MANCHESTER => MANCHESTER_B,
DECODE_DATA => sensor_temp_b
);
----------------------------------------------------------------------------------
Inst_decoding_crc_3 : decoding_crc
port map(
CLK => CLK_100M,
RST => sys_rst,
MANCHESTER => MANCHESTER_C,
DECODE_DATA => sensor_temp_c
);
----------------------------------------------------------------------------------
Inst_Coder_detec_1 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_a_rst,
CODER_QEA => CODER_QEA_A,
CODER_QEB => CODER_QEB_A,
CODER_CNT_OUT => coder_cnt_a
);
----------------------------------------------------------------------------------
Inst_Coder_detec_2 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_b_rst,
CODER_QEA => CODER_QEA_B,
CODER_QEB => CODER_QEB_B,
CODER_CNT_OUT => coder_cnt_b
);
----------------------------------------------------------------------------------
Inst_Coder_detec_3 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_c_rst,
CODER_QEA => CODER_QEA_C,
CODER_QEB => CODER_QEB_C,
CODER_CNT_OUT => coder_cnt_c
);
----------------------------------------------------------------------------------
Inst_Coder_detec_4 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_d_rst,
CODER_QEA => CODER_QEA_D,
CODER_QEB => CODER_QEB_D,
CODER_CNT_OUT => coder_cnt_d
);
----------------------------------------------------------------------------------
Inst_Coder_detec_5 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_e_rst,
CODER_QEA => CODER_QEA_E,
CODER_QEB => CODER_QEB_E,
CODER_CNT_OUT => coder_cnt_e
);
----------------------------------------------------------------------------------
Inst_Coder_detec_6 : quad_encoder
port map(
CLK => CLK_50M,
RST => sys_rst,
CLEAR_CNT => coder_f_rst,
CODER_QEA => CODER_QEA_F,
CODER_QEB => CODER_QEB_F,
CODER_CNT_OUT => coder_cnt_f
);
----------------------------------------------------------------------------------
Inst_Write_sensor : Write_sensor
port map(
CLK => CLK_100M,
RST => sys_rst,
DECODE_DATE_A => sensor_temp_a,
DECODE_DATE_B => sensor_temp_b,
DECODE_DATE_C => sensor_temp_c,
FPGA_WRITE_RAM1_ADDR => ram1_write,
FPGA_WRITE_RAM1_DATE => ram1_dina
);
----------------------------------------------------------------------------------
Inst_Write_coder : Write_coder
port map(
CLK => CLK_100M,
RST => sys_rst,
CODER_CNT_A => coder_cnt_a,
CODER_CNT_B => coder_cnt_b,
CODER_CNT_C => coder_cnt_c,
CODER_CNT_D => coder_cnt_d,
CODER_CNT_E => coder_cnt_e,
CODER_CNT_F => coder_cnt_f,
FPGA_WRITE_RAM2_ADDR => ram2_write,
FPGA_WRITE_RAM2_DATE => ram2_dina
);
----------------------------------------------------------------------------------
Inst_sram_1 : sram
port map(
clka => CLK_100M, ena => ram12_ena, wea => ram_en, addra => ram1_write, dina => ram1_dina, clkb => CLK_ARM, enb => ram1_read, addrb => ram12_addrb, doutb => ram1_doutb
);
----------------------------------------------------------------------------------
Inst_sram_2 : sram
port map(
clka => CLK_100M, ena => ram12_ena, wea => ram_en, addra => ram2_write, dina => ram2_dina, clkb => CLK_ARM, enb => ram2_read, addrb => ram12_addrb, doutb => ram2_doutb
);
----------------------------------------------------------------------------------
Inst_sram_3 : ram_3
port map(
clka => CLK_ARM, ena => ram12_ena, wea => ram3_write,
addra => ram3_addra, dina => ram3_dina, clkb => CLK_100M, enb => ram3_read,
addrb => ram3_addrb, doutb => ram3_doutb
);
----------------------------------------------------------------------------------
Inst_ARM_EPI : ARM_EPI
port map(
CLK => CLK_ARM,
ARM_FRAME => ARM_FRAME,
ARM_WRITE => ARM_WRITE,
ARM_READ => ARM_READ,
ARM_ADDR => ARM_ADDR,
SENSOR_DATA => ram1_doutb,
CODER_DATA => ram2_doutb,
RAM3_WEA => ram3_write,
RAM1_ENB => ram1_read,
RAM2_ENB => ram2_read,
RAM3_DINA => ram3_dina,
RAM3_ADDRA => ram3_addra,
RAM12_ADDRA => ram12_addrb,
ARM_FPGA_DATA => ARM_FPGA_DATA
);
----------------------------------------------------------------------------------
Inst_read_ram : read_ram3
port map(
CLK => CLK_100M,
-- RST => sys_rst,
RAM3_RD_START => ARM_WRITE_OVER,
RAM3_ENB => ram3_read,
RAM3_ADDRB => ram3_addrb,
RAM3_ADDRB_REG => channel_addr
);
----------------------------------------------------------------------------------
Inst_Coder_rst : Coder_rst
port map(
CLK => CLK_100M,
RST => sys_rst,
CHANNEL_ADDR => channel_addr,
CODER_RST_DATA_IN => ram3_doutb,
CODER_RST_DATA_OUT => coder_rst_num
);
----------------------------------------------------------------------------------
Inst_interrupt : interrupt
port map(
CLK => CLK_25M,
RST => sys_rst,
INTERRUPT_OUT => interrupt_for_arm_reg
);
----------------------------------------------------------------------------------
Inst_pwm_12 : pwm_12
port map(
CLK => CLK_100M,
RST => sys_rst,
FREQ_DUTY_DATA => ram3_doutb,
CHANNEL_ADDR => channel_addr,
DIR_POSITIVE => PWM_DIR_POSITIVE,
DIR_NEGATIVE => PWM_DIR_NEGATIVE,
PWM_OUT => PWM_OUT
);
----------------------------------------------------------------------------------
Inst_Pulse_16 : Pulse_16
port map(
CLK => CLK_100M,
RST => sys_rst,
INTERRUPT_IN => interrupt_for_arm_reg,
PULSE_DATA_IN => ram3_doutb,
CHANNEL_ADDR => channel_addr,
PULSE_EN => PULSE_OUT_EN,
PULSE_DIR => PULSE_OUT_DIR,
PULSE_OUT => PULSE_OUT
);
----------------------------------------------------------------------------------
end Behavioral; ⌨️ 快捷键说明
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