📄 dfbc94567928dc8a62ce75cb7b66fb2dd347da47.svn-base

📁 FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的
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----------------------------------------------------------------------------------
-- Company: 			Han'slaser
-- Engineer:  			Zhouj110624
-- Create Date:    	16:29:22 12/28/2012 
-- Design Name: 		G510_106T_1_1
-- Module Name:    	G510_106T_1_1 - Behavioral 
-- Project Name: 		G510_106T_1_1
-- Target Devices: 	
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity G510_106A is
	port(
--In------------------------------------------------------------------------------
		CLK					:	in		std_logic;
		ARM_RST				:	in		std_logic;
		CLK_ARM				:	in		std_logic;
		ARM_WRITE_OVER		:	in		std_logic;
		ARM_FRAME			:	in		std_logic;
		ARM_WRITE			:	in		std_logic;
		ARM_READ				:	in		std_logic;
		ARM_ADDR				:	in		std_logic_vector(11 downto 0);
----------------------------------------------------------------------------------	
		MANCHESTER_A		:	in		std_logic;
		MANCHESTER_B		:	in		std_logic;
		MANCHESTER_C		:	in		std_logic;
----------------------------------------------------------------------------------
		CODER_QEA_A			:	in		std_logic;
		CODER_QEB_A			:	in		std_logic;
		CODER_QEA_B			:	in		std_logic;
		CODER_QEB_B			:	in		std_logic;
		CODER_QEA_C			:	in		std_logic;
		CODER_QEB_C			:	in		std_logic;
		CODER_QEA_D			:	in		std_logic;
		CODER_QEB_D			:	in		std_logic;
		CODER_QEA_E			:	in		std_logic;
		CODER_QEB_E			:	in		std_logic;
		CODER_QEA_F			:	in		std_logic;  
		CODER_QEB_F			:	in		std_logic;
--Out-----------------------------------------------------------------------------	
		PULSE_OUT_EN		:	out	std_logic_vector(15 downto 0);
		PULSE_OUT_DIR		:	out	std_logic_vector(15 downto 0);
		PULSE_OUT			:	out	std_logic_vector(15 downto 0);
		PWM_DIR_POSITIVE	:	out	std_logic_vector(11 downto 0);
		PWM_DIR_NEGATIVE	:	out 	std_logic_vector(11 downto 0);
		PWM_OUT				:	out	std_logic_vector(11 downto 0);
		INTERRUPT_FOR_ARM	:	out	std_logic;
--Inout---------------------------------------------------------------------------		
		ARM_FPGA_DATA		:	inout	std_logic_vector(15 downto 0)
		);
end G510_106A;

architecture Behavioral of G510_106A is
--component-----------------------------------------------------------------------
----------------------------------------------------------------------------------
component System_rst is
    Port ( 
				CLK			: in	std_logic;
--				LOCKED_OUT	: in	std_logic;
				ARM_RST 		: in	STD_LOGIC;
				SYS_RST 		: out STD_LOGIC
			);
end component;
----------------------------------------------------------------------------------
component decoding_crc is
	port(
			CLK 			: in  STD_LOGIC;
			RST			: in	std_logic;
         MANCHESTER	: in  STD_LOGIC;
         DECODE_DATA : out STD_LOGIC_VECTOR (31 downto 0)
		);
end component;
----------------------------------------------------------------------------------
--component Orthogonal is
--	port(
--		CLK				:	in	std_logic;
--		RST				:	in	std_logic;
--		CLEAR_CNT		:	in	std_logic;
--		CODER_QEA		:	in 	std_logic;
--		CODER_QEB		:	in	std_logic;
--		CODER_CNT_OUT	:	out std_logic_vector(31 downto 0)
--		);
--end component;

component quad_encoder is    Port ( 				CLK 				: in std_logic;			RST				: in std_logic;			CLEAR_CNT		: in std_logic;			CODER_QEA 		: in std_logic;			CODER_QEB 		: in std_logic;--			data_z 			: in std_logic;--			Poc_pulse		:	out std_logic;--			Poc_dir			: out std_logic;			CODER_CNT_OUT 	: out std_logic_vector (31 downto 0)		);end component;
----------------------------------------------------------------------------------
component Write_sensor is 
	port(
		CLK						:	in	std_logic;
		RST						:	in	std_logic;
		DECODE_DATE_A			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		DECODE_DATE_B			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		DECODE_DATE_C			:	in	std_logic_vector(31 downto 0);--曼彻斯特解码后的数据
		FPGA_WRITE_RAM1_ADDR	:	out std_logic_vector(10 downto 0);--输出fpga写sram地址
		FPGA_WRITE_RAM1_DATE	:	out std_logic_vector(31 downto 0)--输出fpga写sram数据
		);
end component;
----------------------------------------------------------------------------------
component Write_coder is
	port(
		CLK						: in	std_logic;
		RST						: in	std_logic;
		CODER_CNT_A				: in	std_logic_vector(31 downto 0);--编码器脉冲计数值输入
		CODER_CNT_B				: in	std_logic_vector(31 downto 0);
		CODER_CNT_C				: in	std_logic_vector(31 downto 0);
		CODER_CNT_D				: in	std_logic_vector(31 downto 0);--编码器脉冲计数值输入
		CODER_CNT_E				: in	std_logic_vector(31 downto 0);
		CODER_CNT_F				: in	std_logic_vector(31 downto 0);
		FPGA_WRITE_RAM2_ADDR	: out std_logic_vector(10 downto 0);--输出fpga写sram地址
		FPGA_WRITE_RAM2_DATE	: out std_logic_vector(31 downto 0)--输出fpga写sram数据
		);
end component;
----------------------------------------------------------------------------------
component ARM_EPI is
    Port ( 	
			CLK 				: in		std_logic;--ARM EPI接口传输时钟
			ARM_FRAME 		: in  	STD_LOGIC;--帧
			ARM_WRITE 		: in  	STD_LOGIC;--ARM向FPGA中写
			ARM_READ 		: in  	STD_LOGIC;--ARM从FPGA中读				
			ARM_ADDR 		: in  	STD_LOGIC_VECTOR (11 downto 0);--ARM送读写地址
			SENSOR_DATA		: in  	std_logic_vector(15 downto 0);
			CODER_DATA		: in  	std_logic_vector(15 downto 0);
			RAM3_WEA			: out		std_logic_vector(0 downto 0);
			RAM1_ENB			: out 	std_logic;
			RAM2_ENB			: out 	std_logic;
			RAM3_DINA		: out 	std_logic_vector(15 downto 0);
			RAM3_ADDRA		: out 	std_logic_vector(11 downto 0);
			RAM12_ADDRA		: out 	std_logic_vector(11 downto 0);
			ARM_FPGA_DATA	: inout 	STD_LOGIC_VECTOR (15 downto 0));--ARM与FPGA通信双向口
end component;
----------------------------------------------------------------------------------
component read_ram3 is	
	port(		CLK				: in	std_logic;
--		RST				: in	std_logic;		RAM3_RD_START	: in	std_logic;		RAM3_ENB			: out	std_logic;		RAM3_ADDRB		: out	std_logic_vector(10 downto 0);
		RAM3_ADDRB_REG	: out	std_logic_vector(10 downto 0)		);
end component;
----------------------------------------------------------------------------------
component Coder_rst is 
	port(
		CLK						: in	std_logic;
		RST						: in	std_logic;
		CHANNEL_ADDR			: in	std_logic_vector(10 downto 0);
		CODER_RST_DATA_IN		: in	std_logic_vector(31 downto 0);
		CODER_RST_DATA_OUT	: out	std_logic_vector(5 downto 0)
		);
end component;
----------------------------------------------------------------------------------
component interrupt is
    Port ( 	
			CLK 				: 	in	STD_LOGIC;
			RST 				:	in	std_logic;			INTERRUPT_OUT 	: 	out STD_LOGIC
		);
end component;
----------------------------------------------------------------------------------
component pwm_12 is 
    Port ( 	
			CLK 				: in	STD_LOGIC;
			RST				: in	std_logic;
			FREQ_DUTY_DATA	: in	STD_LOGIC_VECTOR( 31 downto 0 );--输入占空比数据、频率数据和使能方向信号
			CHANNEL_ADDR	: in	std_logic_vector(10 downto 0);--通道地址
			DIR_POSITIVE	: out std_logic_vector(11 downto 0);--输出12路方向信号			DIR_NEGATIVE	: out std_logic_vector(11 downto 0);--输出12路方向信号
			PWM_OUT			: out	STD_LOGIC_VECTOR (11 downto 0)--输出12路PWM信号		   );
end component;
----------------------------------------------------------------------------------
component Pulse_16 is
	port(		CLK				: in	std_logic;
		RST				: in	std_logic;
		INTERRUPT_IN	: in	std_logic;
		PULSE_DATA_IN	: in	std_logic_vector(31 downto 0);--输入脉冲数据，高16位为脉冲数目数据，低16位为地址、使能和方向。
		CHANNEL_ADDR	: in	std_logic_vector(10 downto 0);
		PULSE_EN			: out std_logic_vector(15 downto 0);--输出16路使能信号
		PULSE_DIR		: out std_logic_vector(15 downto 0);--输出16路方向信号
		PULSE_OUT		: out std_logic_vector(15 downto 0)--输出16路脉冲信号		);
end component;
----------------------------------------------------------------------------------
component my_dcm	port(		CLKIN_IN 			: IN std_logic;    
		RST_IN				: IN std_logic; 		CLKFX_OUT 			: OUT std_logic;		CLKIN_IBUFG_OUT 	: OUT std_logic;		CLK0_OUT 			: OUT std_logic;		CLK2X_OUT 			: OUT std_logic		);end component;
----------------------------------------------------------------------------------
component sram	port (			clka		: in std_logic;			ena		: in std_logic;			wea		: in std_logic_vector(0 downto 0);			addra		: in std_logic_vector(10 downto 0);			dina		: in std_logic_vector(31 downto 0);			clkb		: in std_logic;			enb		: in std_logic;			addrb		: in std_logic_vector(11 downto 0);			doutb		: out std_logic_vector(15 downto 0));end component;
component ram_3
	port (		clka		: in std_logic;		ena		: in std_logic;		wea		: in std_logic_vector(0 downto 0);		addra		: in std_logic_vector(11 downto 0);		dina		: in std_logic_vector(15 downto 0);		clkb		: in std_logic;		enb		: in std_logic;		addrb		: in std_logic_vector(10 downto 0);		doutb		: out std_logic_vector(31 downto 0));
end component;
----------------------------------------------------------------------------------
--signal--------------------------------------------------------------------------
--System_rst----------------------------------------------------------------------
	signal sys_rst						:	std_logic := '0';
--DCM_out-------------------------------------------------------------------------
	constant DCM_RST						: std_logic := '0';
	signal CLK_25M						: std_logic;--	signal CLK_25M_buf				: std_logic;	signal CLK_50M						: std_logic;	signal CLK_100M					: std_logic;
--	signal LOCKED_OUT					: std_logic;
--decoding_crc->write_sensor------------------------------------------------------
	signal sensor_temp_a				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal sensor_temp_b				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal sensor_temp_c				:	std_logic_vector(31 downto 0) := ( others => '0' );
--Coder_detec->write_coder--------------------------------------------------------
	signal coder_cnt_a				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal coder_cnt_b				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal coder_cnt_c				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal coder_cnt_d				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal coder_cnt_e				:	std_logic_vector(31 downto 0) := ( others => '0' );
	signal coder_cnt_f				:	std_logic_vector(31 downto 0) := ( others => '0' );
--write_sensor->sram--------------------------------------------------------------
	signal ram1_write					:	std_logic_vector(10 downto 0) := ( others => '0' );
	signal ram1_dina					:	std_logic_vector(31 downto 0) := ( others => '0' );
--write_coder->sram---------------------------------------------------------------
	signal ram2_write					:	std_logic_vector(10 downto 0) := ( others => '0' );
	signal ram2_dina					:	std_logic_vector(31 downto 0) := ( others => '0' );
--sram->ARM_EPI-------------------------------------------------------------------
	signal ram1_doutb					:	std_logic_vector(15 downto 0) := ( others => '0' );
	signal ram2_doutb					:	std_logic_vector(15 downto 0) := ( others => '0' );
--ARM_EPI->sram-------------------------------------------------------------------
	signal ram1_read					:	std_logic := '0';
	signal ram2_read					:	std_logic := '0';
	signal ram3_write					:	std_logic_vector(0 downto 0) := ( others => '0' );
	signal ram3_addra					:	std_logic_vector(11 downto 0) := ( others => '0' );
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