5070909f673bf1191b0a9fa33d7134702bc9305f.svn-base

来自「FPGA与ARM EPI通信，控制16路步进电机和12路DC马达 VHDL编写的」· SVN-BASE 代码 · 共 43 行

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-- Purpose : synthesizable CRC function
--   * polynomial: (0 4 5 8)
--   * data width: 1
-- convention: the first serial bit is D[0]
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

package PCK_CRC8_D1 is
  function nextCRC8_D1
    (Data: std_logic;--当前位
     crc:  std_logic_vector(7 downto 0))--校验完前一位所得的CRC校验码（若当期位为第一位，则CRC为0）
    return std_logic_vector;
end PCK_CRC8_D1;
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package body PCK_CRC8_D1 is
  function nextCRC8_D1
    (Data: std_logic;
     crc:  std_logic_vector(7 downto 0))
    return std_logic_vector is

    variable d:      std_logic_vector(0 downto 0);
    variable c:      std_logic_vector(7 downto 0);
    variable newcrc: std_logic_vector(7 downto 0);
--------------------------------------------------------------------------------
  begin
    d(0) := Data;
    c := crc;

    newcrc(0) := d(0) xor c(7);
    newcrc(1) := c(0);
    newcrc(2) := c(1);
    newcrc(3) := c(2);
    newcrc(4) := d(0) xor c(3) xor c(7);
    newcrc(5) := d(0) xor c(4) xor c(7);
    newcrc(6) := c(5);
    newcrc(7) := c(6);
    return newcrc;
  end nextCRC8_D1;

end PCK_CRC8_D1;