📄 1401bfbf62ddc3ecaadc2dc343dc0aa8ee4281a3.svn-base
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----------------------------------------------------------------------------------
-- Company: Han'slaser
-- Engineer: Zhouj110624
-- Create Date: 14:17:13 09/24/2012
-- Design Name: pwm_12
-- Module Name: pwm_12 - Behavioral
-- Project Name: pwm_12
-- Target Devices:
-- 功能说明：12路PWM信号发生模块，输入32位数据DUTY_NUM_pul，
-- 由占空比数据、频率数据、地址数据和使能方向信号组成，
-- 输出为占空比和频率可调的12路PWM信号和使能、方向信号
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity pwm_12 is
Port (
CLK : in STD_LOGIC;
RST : in std_logic;
FREQ_DUTY_DATA : in STD_LOGIC_VECTOR( 31 downto 0 );--输入占空比数据、频率数据和使能方向信号
CHANNEL_ADDR : in std_logic_vector(10 downto 0);--通道地址
DIR_POSITIVE : out std_logic_vector(11 downto 0);--输出12路方向信号 DIR_NEGATIVE : out std_logic_vector(11 downto 0);--输出12路方向信号
PWM_OUT : out STD_LOGIC_VECTOR (11 downto 0)--输出12路PWM信号
);
end pwm_12;
----------------------------------------------------------------------------------
architecture Behavioral of pwm_12 is
component pwm is
Port (
CLK : in STD_LOGIC;
RST : in std_logic;
CLK_10MHz : in std_logic;
PWM_OUT_EN : in std_logic;
FREQUENCY_NUM : in std_logic_vector(15 downto 0);
DUTY_NUM : in STD_LOGIC_VECTOR (13 downto 0);
PWM_OUT : out STD_LOGIC
);
end component;
----------------------------------------------------------------------------------
signal CLK_10MHz : std_logic :='0';
signal divide_cnt : std_logic_vector(3 downto 0) := (others => '0');
signal channel_addr_reg : std_logic_vector(10 downto 0) := (others => '0');--PWM通道地址
signal channel_en : std_logic := '0';
signal channel_en_reg : std_logic_vector(11 downto 0) := (others => '0');
signal channel_dir : std_logic := '0';
signal channel_dir_p : std_logic_vector(11 downto 0) := (others => '0');signal channel_dir_n : std_logic_vector(11 downto 0) := (others => '0');
----------------------------------------------------------------------------------
signal pwm_duty : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_1 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_2 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_3 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_4 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_5 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_6 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_7 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_8 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_9 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_10 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_11 : std_logic_vector(13 downto 0) := (others => '0');
signal pwm_duty_12 : std_logic_vector(13 downto 0) := (others => '0');
----------------------------------------------------------------------------------
signal pwm_frequency : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_1 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_2 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_3 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_4 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_5 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_6 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_7 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_8 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_9 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_10 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_11 : std_logic_vector(15 downto 0) := (others => '0');
signal pwm_frequency_12 : std_logic_vector(15 downto 0) := (others => '0');
----------------------------------------------------------------------------------
begin
DIR_POSITIVE <= channel_dir_p; DIR_NEGATIVE <= channel_dir_n;
----------------------------------------------------------------------------------
--输入数据类型判断，Sbc_input_en不为‘1’，不接收输入数据
------------------------------------------------------------------------------------
Pr_in :
process(CLK)
begin
if rising_edge(CLK) then
-- if RST = '1' then-- pwm_duty <= (others => '0');-- pwm_frequency <= (others => '0');-- channel_addr_reg <= (others => '0');-- channel_en <= '0';-- channel_dir <= '0';
-- else
if (CHANNEL_ADDR(10 downto 4) = "1000010")then
pwm_duty <= FREQ_DUTY_DATA( 31 downto 18 );--取占空比数据
pwm_frequency <= FREQ_DUTY_DATA( 15 downto 0 );--取频率数据
channel_addr_reg <= CHANNEL_ADDR( 10 downto 0 );--取地址
channel_en <= FREQ_DUTY_DATA( 17 );
channel_dir <= FREQ_DUTY_DATA( 16 );
else
null;
end if;
-- end if;
end if;
end process;
----------------------------------------------------------------------------------
--分频进程，由25MHz分至500KHz
----------------------------------------------------------------------------------
Pr_div :
process(CLK) begin if rising_edge(CLK) then
if RST = '1' then
divide_cnt <= (others => '0'); CLK_10MHz <= '0';
else if divide_cnt < "1000" then--8 divide_cnt <=divide_cnt + 1; CLK_10MHz <= '0'; elsif divide_cnt = "1000" then--8 CLK_10MHz <= '1'; divide_cnt <=divide_cnt + 1; else divide_cnt <= (others => '0'); CLK_10MHz <= '0'; end if;
end if; end if; end process;
----------------------------------------------------------------------------------
--判断通道地址进程
----------------------------------------------------------------------------------
Pr_judge :
process(CLK)
begin
if rising_edge(CLK) then
case channel_addr_reg is
when "10000100000" => --0
channel_en_reg( 0 ) <= channel_en;
pwm_frequency_1 <= pwm_frequency;
pwm_duty_1 <= pwm_duty;
channel_dir_p( 0 ) <= channel_dir; channel_dir_n( 0 ) <= not channel_dir;
when "10000100001" => --1
channel_en_reg( 1 ) <= channel_en;
pwm_frequency_2 <= pwm_frequency;
pwm_duty_2 <= pwm_duty;
channel_dir_p( 1 ) <= channel_dir; channel_dir_n( 1 ) <= not channel_dir;
when "10000100010" => --2
channel_en_reg( 2 ) <= channel_en;
pwm_frequency_3 <= pwm_frequency;
pwm_duty_3 <= pwm_duty;
channel_dir_p( 2 ) <= channel_dir; channel_dir_n( 2 ) <= not channel_dir;
when "10000100011" => --3
channel_en_reg( 3 ) <= channel_en;
pwm_frequency_4 <= pwm_frequency;
pwm_duty_4 <= pwm_duty;
channel_dir_p( 3 ) <= channel_dir; channel_dir_n( 3 ) <= not channel_dir;
when "10000100100" => --4
channel_en_reg( 4 ) <= channel_en;
pwm_frequency_5 <= pwm_frequency;
pwm_duty_5 <= pwm_duty;
channel_dir_p( 4 ) <= channel_dir; channel_dir_n( 4 ) <= not channel_dir;
when "10000100101" => --5
channel_en_reg( 5 ) <= channel_en;
pwm_frequency_6 <= pwm_frequency;
pwm_duty_6 <= pwm_duty;
channel_dir_p( 5 ) <= channel_dir; channel_dir_n( 5 ) <= not channel_dir;
when "10000100110" => --6
channel_en_reg( 6 ) <= channel_en;
pwm_frequency_7 <= pwm_frequency;
pwm_duty_7 <= pwm_duty;
channel_dir_p( 6 ) <= channel_dir; channel_dir_n( 6 ) <= not channel_dir;
when "10000100111" => --7
channel_en_reg( 7 ) <= channel_en;
pwm_frequency_8 <= pwm_frequency;
pwm_duty_8 <= pwm_duty;
channel_dir_p( 7 ) <= channel_dir; channel_dir_n( 7 ) <= not channel_dir;
when "10000101000" => --8
channel_en_reg( 8 ) <= channel_en;
pwm_frequency_9 <= pwm_frequency;
pwm_duty_9 <= pwm_duty;
channel_dir_p( 8 ) <= channel_dir; channel_dir_n( 8 ) <= not channel_dir;
when "10000101001" => --9
channel_en_reg( 9 ) <= channel_en;
pwm_frequency_10 <= pwm_frequency;
pwm_duty_10 <= pwm_duty;
channel_dir_p( 9 ) <= channel_dir; channel_dir_n( 9 ) <= not channel_dir;
when "10000101010" => --10
channel_en_reg( 10 ) <= channel_en;
pwm_frequency_11 <= pwm_frequency;
pwm_duty_11 <= pwm_duty;
channel_dir_p( 10 ) <= channel_dir; channel_dir_n( 10 ) <= not channel_dir;
when "10000101011" => --11
channel_en_reg( 11 ) <= channel_en;
pwm_frequency_12 <= pwm_frequency;
pwm_duty_12 <= pwm_duty;
channel_dir_p( 11 ) <= channel_dir; channel_dir_n( 11 ) <= not channel_dir;
when others => null;
end case;
end if;
end process;
----------------------------------------------------------------------------------
--12路pwm例化
----------------------------------------------------------------------------------
inst_pwm1 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(0),
FREQUENCY_NUM => pwm_frequency_1,
DUTY_NUM => pwm_duty_1,
PWM_OUT => PWM_OUT( 0 )
);
----------------------------------------------------------------------------------
inst_pwm2 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(1),
FREQUENCY_NUM => pwm_frequency_2,
DUTY_NUM => pwm_duty_2,
PWM_OUT => PWM_OUT( 1 )
);
----------------------------------------------------------------------------------
inst_pwm3 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(2),
FREQUENCY_NUM => pwm_frequency_3,
DUTY_NUM => pwm_duty_3,
PWM_OUT => PWM_OUT( 2 )
);
----------------------------------------------------------------------------------
inst_pwm4 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(3),
FREQUENCY_NUM => pwm_frequency_4,
DUTY_NUM => pwm_duty_4,
PWM_OUT => PWM_OUT( 3 )
);
----------------------------------------------------------------------------------
inst_pwm5 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(4),
FREQUENCY_NUM => pwm_frequency_5,
DUTY_NUM => pwm_duty_5,
PWM_OUT => PWM_OUT( 4 )
);
----------------------------------------------------------------------------------
inst_pwm6 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(5),
FREQUENCY_NUM => pwm_frequency_6,
DUTY_NUM => pwm_duty_6,
PWM_OUT => PWM_OUT( 5 )
);
----------------------------------------------------------------------------------
inst_pwm7 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(6),
FREQUENCY_NUM => pwm_frequency_7,
DUTY_NUM => pwm_duty_7,
PWM_OUT => PWM_OUT( 6 )
);
----------------------------------------------------------------------------------
inst_pwm8 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(7),
FREQUENCY_NUM => pwm_frequency_8,
DUTY_NUM => pwm_duty_8,
PWM_OUT => PWM_OUT( 7 )
);
----------------------------------------------------------------------------------
inst_pwm9 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(8),
FREQUENCY_NUM => pwm_frequency_9,
DUTY_NUM => pwm_duty_9,
PWM_OUT => PWM_OUT( 8 )
);
----------------------------------------------------------------------------------
inst_pwm10 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(9),
FREQUENCY_NUM => pwm_frequency_10,
DUTY_NUM => pwm_duty_10,
PWM_OUT => PWM_OUT( 9 )
);
----------------------------------------------------------------------------------
inst_pwm11 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(10),
FREQUENCY_NUM => pwm_frequency_11,
DUTY_NUM => pwm_duty_11,
PWM_OUT => PWM_OUT( 10 )
);
----------------------------------------------------------------------------------
inst_pwm12 : pwm
port map(
CLK => CLK,
RST => RST,
CLK_10MHz => CLK_10MHz,
PWM_OUT_EN => channel_en_reg(11),
FREQUENCY_NUM => pwm_frequency_12,
DUTY_NUM => pwm_duty_12,
PWM_OUT => PWM_OUT( 11 )
);
----------------------------------------------------------------------------------
end Behavioral;
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